Lines Matching defs:pipe_config
3574 struct intel_crtc_config *pipe_config = &crtc->config;
3586 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3587 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3946 struct intel_crtc_config *pipe_config)
3953 pipe_name(pipe), pipe_config->fdi_lanes);
3954 if (pipe_config->fdi_lanes > 4) {
3956 pipe_name(pipe), pipe_config->fdi_lanes);
3961 if (pipe_config->fdi_lanes > 2) {
3963 pipe_config->fdi_lanes);
3979 pipe_config->fdi_lanes > 2) {
3981 pipe_name(pipe), pipe_config->fdi_lanes);
3988 if (pipe_config->fdi_lanes > 2) {
3990 pipe_name(pipe), pipe_config->fdi_lanes);
4009 struct intel_crtc_config *pipe_config)
4012 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4027 fdi_dotclock /= pipe_config->pixel_multiplier;
4033 pipe_config->pipe_bpp);
4035 pipe_config->fdi_lanes = lane;
4037 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4038 link_bw, &pipe_config->fdi_m_n);
4041 intel_crtc->pipe, pipe_config);
4042 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4043 pipe_config->pipe_bpp -= 2*3;
4045 pipe_config->pipe_bpp);
4047 pipe_config->bw_constrained = true;
4059 struct intel_crtc_config *pipe_config)
4061 pipe_config->ips_enabled = i915_enable_ips &&
4063 pipe_config->pipe_bpp == 24;
4067 struct intel_crtc_config *pipe_config)
4070 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4074 if (pipe_config->requested_mode.clock * 3
4082 if (!pipe_config->timings_set)
4092 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4093 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4094 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4097 pipe_config->pipe_bpp = 8*3;
4101 hsw_compute_ips_config(crtc, pipe_config);
4106 pipe_config->shared_dpll = crtc->config.shared_dpll;
4108 if (pipe_config->has_pch_encoder)
4109 return ironlake_fdi_compute_config(crtc, pipe_config);
4744 struct intel_crtc_config *pipe_config)
4748 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4752 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4753 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4755 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4756 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4758 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4759 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4762 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4763 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4765 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4766 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4768 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4769 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4772 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4773 pipe_config->adjusted_mode.crtc_vtotal += 1;
4774 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4778 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4779 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4961 struct intel_crtc_config *pipe_config)
4980 pipe_config->gmch_pfit.control = tmp;
4981 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4983 pipe_config->gmch_pfit.lvds_border_bits =
4988 struct intel_crtc_config *pipe_config)
4994 pipe_config->cpu_transcoder = (enum transcoder)crtc->pipe;
4995 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5001 intel_get_pipe_timings(crtc, pipe_config);
5003 i9xx_get_pfit_config(crtc, pipe_config);
5007 pipe_config->pixel_multiplier =
5012 pipe_config->pixel_multiplier =
5019 pipe_config->pixel_multiplier = 1;
5838 struct intel_crtc_config *pipe_config)
5842 enum transcoder transcoder = pipe_config->cpu_transcoder;
5844 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5845 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5846 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5848 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5849 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5854 struct intel_crtc_config *pipe_config)
5863 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5864 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5878 struct intel_crtc_config *pipe_config)
5884 pipe_config->cpu_transcoder = (enum transcoder)crtc->pipe;
5885 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5895 pipe_config->has_pch_encoder = true;
5898 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5901 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5905 pipe_config->pixel_multiplier = 1;
5908 pipe_config->shared_dpll = (enum intel_dpll_id)crtc->pipe;
5912 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5914 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5917 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5920 &pipe_config->dpll_hw_state));
5922 pipe_config->pixel_multiplier = 1;
5925 intel_get_pipe_timings(crtc, pipe_config);
5927 ironlake_get_pfit_config(crtc, pipe_config);
5993 struct intel_crtc_config *pipe_config)
6000 pipe_config->cpu_transcoder = (enum transcoder)crtc->pipe;
6001 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6022 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6026 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6029 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
6038 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6041 pipe_config->has_pch_encoder = true;
6044 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6047 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6050 intel_get_pipe_timings(crtc, pipe_config);
6054 ironlake_get_pfit_config(crtc, pipe_config);
6056 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6059 pipe_config->pixel_multiplier = 1;
7708 struct intel_crtc_config *pipe_config)
7710 int bpp = pipe_config->pipe_bpp;
7721 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7728 pipe_config->pipe_bpp = 24;
7735 struct intel_crtc_config *pipe_config)
7777 pipe_config->pipe_bpp = bpp;
7786 connected_sink_compute_bpp(connector, pipe_config);
7793 struct intel_crtc_config *pipe_config,
7799 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7801 pipe_config->pipe_bpp, pipe_config->dither);
7803 pipe_config->has_pch_encoder,
7804 pipe_config->fdi_lanes,
7805 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7806 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7807 pipe_config->fdi_m_n.tu);
7809 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7811 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7813 pipe_config->gmch_pfit.control,
7814 pipe_config->gmch_pfit.pgm_ratios,
7815 pipe_config->gmch_pfit.lvds_border_bits);
7817 pipe_config->pch_pfit.pos,
7818 pipe_config->pch_pfit.size);
7819 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
7849 struct intel_crtc_config *pipe_config;
7858 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7859 if (!pipe_config)
7862 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7863 drm_mode_copy(&pipe_config->requested_mode, mode);
7864 pipe_config->cpu_transcoder = (enum transcoder)to_intel_crtc(crtc)->pipe;
7865 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7867 /* Compute a starting value for pipe_config->pipe_bpp taking the source
7872 fb, pipe_config);
7878 pipe_config->port_clock = 0;
7879 pipe_config->pixel_multiplier = 1;
7892 if (!(encoder->compute_config(encoder, pipe_config))) {
7902 &pipe_config->requested_mode,
7903 &pipe_config->adjusted_mode))) {
7911 if (!pipe_config->port_clock)
7912 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
7914 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
7932 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7934 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7936 return pipe_config;
7938 kfree(pipe_config, sizeof(*pipe_config));
8109 struct intel_crtc_config *pipe_config)
8112 if (current_config->name != pipe_config->name) { \
8116 pipe_config->name); \
8121 if (current_config->name != pipe_config->name) { \
8125 pipe_config->name); \
8130 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8134 pipe_config->name & (mask)); \
8139 ((current_config->quirks | pipe_config->quirks) & (quirk))
8288 struct intel_crtc_config pipe_config;
8295 (void) memset(&pipe_config, 0, sizeof(pipe_config));
8320 &pipe_config);
8333 encoder->get_config(encoder, &pipe_config);
8341 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8343 intel_dump_pipe_config(crtc, &pipe_config,
8417 struct intel_crtc_config *pipe_config = NULL;
8439 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8440 if (!(pipe_config)) {
8442 pipe_config = NULL;
8446 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8465 to_intel_crtc(crtc)->config = *pipe_config;
8491 crtc->hwmode = pipe_config->adjusted_mode;
8508 if (pipe_config)
8509 kfree(pipe_config, sizeof(*pipe_config));