Cross Reference: /solaris-x11-s12/open-src/kernel/i915/src/intel

Lines Matching defs:p1
55 	intel_range_t   dot, vco, n, m, m1, m2, p, p1;
90         .p1 = { .min = 2, .max = 33 },
103         .p1 = { .min = 1, .max = 6 },
116         .p1 = { .min = 1, .max = 8 },
129         .p1 = { .min = 1, .max = 8 },
143 	.p1 = { .min = 1, .max = 3},
159 	.p1 = { .min = 1, .max = 8},
172 	.p1 = { .min = 2, .max = 8 },
186 	.p1 = { .min = 2, .max = 6 },
202         .p1 = { .min = 1, .max = 8 },
215         .p1 = { .min = 1, .max = 8 },
234 	.p1 = { .min = 1, .max = 8 },
247 	.p1 = { .min = 2, .max = 8 },
260 	.p1 = { .min = 2, .max = 8 },
274 	.p1 = { .min = 2,.max = 8 },
287 	.p1 = { .min = 2,.max = 6 },
300 	.p1 = { .min = 1, .max = 3 },
313 	.p1 = { .min = 2, .max = 3 },
326 	.p1 = { .min = 1, .max = 3 },
415 	clock->p = clock->p1 * clock->p2;
428 	clock->p = clock->p1 * clock->p2;
458 	if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
459 		INTELPllInvalid ("p1 out of range\n");
519 				for (clock.p1 = limit->p1.min;
520 					clock.p1 <= limit->p1.max; clock.p1++) {
578 				for (clock.p1 = limit->p1.min;
579 					clock.p1 <= limit->p1.max; clock.p1++) {
637 				for (clock.p1 = limit->p1.max;
638 				     clock.p1 >= limit->p1.min; clock.p1--) {
665 	u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
678 	n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
684 		for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
688 				p = p1 * p2;
698 						if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
710 							bestp1 = p1;
722 	best_clock->p1 = bestp1;
4420 	bestp1 = crtc->config.dpll.p1;
4559 	/* compute bitmask from p1 value */
4561 		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4563 		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4565 			dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4640 		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4642 		if (clock->p1 == 2)
4645 			dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4881 	 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4913 		intel_crtc->config.dpll.p1 = clock.p1;
5528 	 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5670 	/* compute bitmask from p1 value */
5671 	dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5673 	dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5740 		intel_crtc->config.dpll.p1 = clock.p1;
6969 			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6972 			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6998 			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7010 				clock.p1 = 2;
7012 				clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>