Lines Matching defs:base
911 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1399 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1415 crtc->base.base.id);
1431 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1448 crtc->base.base.id);
1842 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1954 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2044 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2060 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2085 * Also update the base address of all primary
2117 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2200 DRM_ERROR("failed to update base address\n");
2266 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2648 struct drm_device *dev = intel_crtc->base.dev;
2685 struct drm_device *dev = intel_crtc->base.dev;
2896 struct drm_device *dev = crtc->base.dev;
3051 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3057 crtc->base.base.id, pll->name);
3067 crtc->base.base.id, pll->name);
3082 crtc->base.base.id,
3094 crtc->base.base.id, pll->name);
3143 struct drm_device *dev = crtc->base.dev;
3168 list_for_each_entry(intel_plane, struct intel_plane, &dev->mode_config.plane_list, base.head)
3170 intel_plane_restore(&intel_plane->base);
3179 list_for_each_entry(intel_plane, struct intel_plane, &dev->mode_config.plane_list, base.head)
3181 intel_plane_disable(&intel_plane->base);
3268 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3273 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3288 struct drm_device *dev = crtc->base.dev;
3374 struct drm_device *dev = crtc->base.dev;
3531 struct drm_device *dev = intel_crtc->base.dev;
3572 struct drm_device *dev = crtc->base.dev;
3687 struct drm_device *dev = crtc->base.dev;
3861 intel_crtc_update_dpms(encoder->base.crtc);
3865 intel_crtc_update_dpms(encoder->base.crtc);
3880 connector->base.base.id,
3881 drm_get_connector_name(&connector->base));
3883 if (connector->base.dpms == DRM_MODE_DPMS_OFF)
3885 if (connector->base.encoder != &encoder->base)
3893 if (!encoder->base.crtc) {
3898 crtc = encoder->base.crtc;
3925 if (encoder->base.crtc)
4011 struct drm_device *dev = intel_crtc->base.dev;
4040 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4069 struct drm_device *dev = crtc->base.dev;
4308 struct drm_device *dev = crtc->base.dev;
4326 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4366 struct drm_device *dev = crtc->base.dev;
4379 struct drm_device *dev = crtc->base.dev;
4407 struct drm_device *dev = crtc->base.dev;
4459 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4460 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4467 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4468 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4488 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4489 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4495 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4528 struct drm_device *dev = crtc->base.dev;
4538 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4539 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4543 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4556 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4586 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4597 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4628 struct drm_device *dev = crtc->base.dev;
4639 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4650 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4661 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4681 struct drm_device *dev = intel_crtc->base.dev;
4746 struct drm_device *dev = crtc->base.dev;
4784 struct drm_device *dev = intel_crtc->base.dev;
4963 struct drm_device *dev = crtc->base.dev;
4990 struct drm_device *dev = crtc->base.dev;
5039 base.head) {
5047 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5184 list_for_each_entry(encoder, struct intel_encoder, &mode_config->encoder_list, base.head) {
5574 struct drm_device *dev = intel_crtc->base.dev;
5617 struct drm_crtc *crtc = &intel_crtc->base;
5840 struct drm_device *dev = crtc->base.dev;
5856 struct drm_device *dev = crtc->base.dev;
5880 struct drm_device *dev = crtc->base.dev;
5937 list_for_each_entry(crtc, struct intel_crtc, &dev->mode_config.crtc_list, base.head) {
5938 if (!crtc->base.enabled)
5995 struct drm_device *dev = crtc->base.dev;
6090 encoder->base.base.id,
6091 drm_get_encoder_name(&encoder->base),
6092 mode->base.id, mode->name);
6096 encoder_funcs = encoder->base.helper_private;
6097 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6348 connector->base.id,
6350 connector->encoder->base.id,
6402 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6407 bool visible = base != 0;
6415 /* On these chipsets we can only modify the base whilst
6418 I915_WRITE(_CURABASE, base);
6432 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6438 bool visible = base != 0;
6442 if (base) {
6455 I915_WRITE(CURBASE(pipe), base);
6458 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6464 bool visible = base != 0;
6468 if (base) {
6482 I915_WRITE(CURBASE_IVB(pipe), base);
6495 u32 base, pos;
6501 base = intel_crtc->cursor_addr;
6503 base = 0;
6506 base = 0;
6508 base = 0;
6512 base = 0;
6521 base = 0;
6528 visible = base != 0;
6534 ivb_update_cursor(crtc, base);
6538 i845_update_cursor(crtc, base);
6540 i9xx_update_cursor(crtc, base);
6572 if (&obj->base == NULL)
6575 if (obj->base.size < width * height * 4) {
6637 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6655 drm_gem_object_unreference_unlocked(&obj->base);
6723 drm_gem_object_unreference_unlocked(&obj->base);
6729 drm_gem_object_unreference_unlocked(&obj->base);
6734 return &intel_fb->base;
6790 fb = &dev_priv->fbdev->ifb.base;
6795 if (obj->base.size < mode->vdisplay * fb->pitches[0])
6809 struct drm_encoder *encoder = &intel_encoder->base;
6816 connector->base.id, drm_get_connector_name(connector),
6817 encoder->base.id, drm_get_encoder_name(encoder));
6915 struct drm_encoder *encoder = &intel_encoder->base;
6919 connector->base.id, drm_get_connector_name(connector),
6920 encoder->base.id, drm_get_encoder_name(encoder));
7153 struct drm_device *dev = obj->base.dev;
7206 drm_gem_object_unreference(&work->pending_flip_obj->base);
7207 drm_gem_object_unreference(&work->old_fb_obj->base);
7241 pollwakeup(&work->event->base.file_priv->drm_pollhead, POLLIN | POLLRDNORM);
7276 /* NB: An MMIO update of the plane base pointer will also
7327 intel_ring_emit(ring, 0); /* aux display base address, unused */
7401 * so we need only reprogram the base address.
7594 drm_gem_object_reference(&work->old_fb_obj->base);
7595 drm_gem_object_reference(&obj->base);
7618 drm_gem_object_unreference(&work->old_fb_obj->base);
7619 drm_gem_object_unreference(&obj->base);
7673 base.head) {
7675 to_intel_encoder(connector->base.encoder);
7679 base.head) {
7681 to_intel_crtc(encoder->base.crtc);
7696 base.head) {
7697 connector->base.encoder = &connector->new_encoder->base;
7701 base.head) {
7702 encoder->base.crtc = &encoder->new_crtc->base;
7713 connector->base.base.id,
7714 drm_get_connector_name(&connector->base));
7717 if (connector->base.display_info.bpc &&
7718 connector->base.display_info.bpc * 3 < bpp) {
7720 bpp, connector->base.display_info.bpc*3);
7721 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7725 if (connector->base.display_info.bpc == 0 && bpp > 24) {
7737 struct drm_device *dev = crtc->base.dev;
7781 base.head) {
7796 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7829 base.head) {
7830 if (&encoder->new_crtc->base != crtc)
7886 base.head) {
7888 if (&encoder->new_crtc->base != crtc)
7900 encoder_funcs = encoder->base.helper_private;
7901 if (!(encoder_funcs->mode_fixup(&encoder->base,
7961 base.head) {
7962 if (connector->base.encoder == &connector->new_encoder->base)
7965 if (connector->base.encoder) {
7966 tmp_crtc = connector->base.encoder->crtc;
7977 base.head) {
7978 if (encoder->base.crtc == &encoder->new_crtc->base)
7981 if (encoder->base.crtc) {
7982 tmp_crtc = encoder->base.crtc;
7993 base.head) {
7997 if (!intel_crtc->base.enabled)
8001 base.head) {
8060 base.head) {
8061 if (!intel_encoder->base.crtc)
8064 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8074 base.head) {
8075 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8089 drm_object_property_set_value(&connector->base,
8103 base.head) \
8214 base.head) {
8219 if (&connector->new_encoder->base != connector->base.encoder)
8231 base.head) {
8237 encoder->base.base.id,
8238 drm_get_encoder_name(&encoder->base));
8240 if (&encoder->new_crtc->base != encoder->base.crtc)
8242 if (encoder->connectors_active && !encoder->base.crtc)
8246 base.head) {
8247 if (connector->base.encoder != &encoder->base)
8250 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8253 if (!!encoder->base.crtc != enabled)
8256 !!encoder->base.crtc, enabled);
8257 if (active && !encoder->base.crtc)
8270 if (!encoder->base.crtc)
8273 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8291 base.head) {
8298 crtc->base.base.id);
8300 if (crtc->active && !crtc->base.enabled)
8304 base.head) {
8305 if (encoder->base.crtc != &crtc->base)
8315 if (enabled != crtc->base.enabled)
8317 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8327 base.head) {
8329 if (encoder->base.crtc != &crtc->base)
8382 base.head) {
8383 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8451 intel_crtc_disable(&intel_crtc->base);
8454 if (intel_crtc->base.enabled)
8455 dev_priv->display.crtc_disable(&intel_crtc->base);
8479 ret = intel_crtc_mode_set(&intel_crtc->base,
8487 dev_priv->display.crtc_enable(&intel_crtc->base);
8589 list_for_each_entry(encoder, struct intel_encoder, &dev->mode_config.encoder_list, base.head) {
8595 list_for_each_entry(connector, struct intel_connector, &dev->mode_config.connector_list, base.head) {
8674 base.head) {
8678 if (set->connectors[ro] == &connector->base) {
8688 connector->base.encoder &&
8689 connector->base.encoder->crtc == set->crtc) {
8693 connector->base.base.id,
8694 drm_get_connector_name(&connector->base));
8698 if (&connector->new_encoder->base != connector->base.encoder) {
8708 base.head) {
8712 new_crtc = connector->new_encoder->base.crtc;
8715 if (set->connectors[ro] == &connector->base)
8720 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8727 connector->base.base.id,
8728 drm_get_connector_name(&connector->base),
8729 new_crtc->base.id);
8734 base.head) {
8737 base.head) {
8748 if (&encoder->new_crtc->base != encoder->base.crtc) {
8775 set->crtc->base.id, set->fb->base.id,
8778 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8798 /* Compute whether we need a full modeset, only an fb base update or no
8826 set->crtc->base.id, ret);
8895 list_for_each_entry(crtc, struct intel_crtc, &dev->mode_config.crtc_list, base.head) {
8954 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8956 (void) drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8973 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8974 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8976 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
9005 struct drm_device *dev = encoder->base.dev;
9011 &dev->mode_config.encoder_list, base.head) {
9152 list_for_each_entry(encoder, struct intel_encoder, &dev->mode_config.encoder_list, base.head) {
9153 encoder->base.possible_crtcs = encoder->crtc_mask;
9154 encoder->base.possible_clones =
9168 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
9180 return drm_gem_handle_create(file, &obj->base, handle);
9284 (void) drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9287 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9305 if (&obj->base == NULL)
9676 connector->base.dpms = DRM_MODE_DPMS_OFF;
9677 connector->base.encoder = NULL;
9679 connector->encoder->base.crtc = NULL;
9693 base.head) {
9695 crt = &connector->base;
9712 struct drm_device *dev = crtc->base.dev;
9731 struct drm_device *dev = crtc->base.dev;
9747 crtc->base.base.id);
9754 dev_priv->display.crtc_disable(&crtc->base);
9759 base.head) {
9760 if (connector->encoder->base.crtc != &crtc->base)
9767 crtc->base.enabled = false;
9781 intel_crtc_update_dpms(&crtc->base);
9783 if (crtc->active != crtc->base.enabled) {
9790 crtc->base.base.id,
9791 crtc->base.enabled ? "enabled" : "disabled",
9794 crtc->base.enabled = crtc->active;
9803 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9805 encoder->base.crtc = NULL;
9813 struct drm_device *dev = encoder->base.dev;
9818 bool has_active_crtc = encoder->base.crtc &&
9819 to_intel_crtc(encoder->base.crtc)->active;
9823 encoder->base.base.id,
9824 drm_get_encoder_name(&encoder->base));
9829 if (encoder->base.crtc) {
9831 encoder->base.base.id,
9832 drm_get_encoder_name(&encoder->base));
9842 base.head) {
9874 base.head) {
9880 crtc->base.enabled = crtc->active;
9883 crtc->base.base.id,
9897 base.head) {
9908 base.head) {
9913 encoder->base.crtc = &crtc->base;
9917 encoder->base.crtc = NULL;
9922 encoder->base.base.id,
9923 drm_get_encoder_name(&encoder->base),
9924 encoder->base.crtc ? "enabled" : "disabled",
9929 base.head) {
9931 connector->base.dpms = DRM_MODE_DPMS_ON;
9933 connector->base.encoder = &connector->encoder->base;
9935 connector->base.dpms = DRM_MODE_DPMS_OFF;
9936 connector->base.encoder = NULL;
9939 connector->base.base.id,
9940 drm_get_connector_name(&connector->base),
9941 connector->base.encoder ? "enabled" : "disabled");
9961 base.head) {
10073 return &intel_attached_encoder(connector)->base;
10080 (void) drm_mode_connector_attach_encoder(&connector->base,
10081 &encoder->base);
10112 u32 base;
10173 error->cursor[i].base = I915_READ(CURBASE(i));
10177 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10260 err_printf(m, " BASE: %08x\n", error->cursor[i].base);