Lines Matching refs:reg
94 u32 reg;
108 for (i=0, reg=DDI_BUF_TRANS(port); i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
109 I915_WRITE(reg, ddi_translations[i]);
110 reg += 4;
149 uint32_t reg = DDI_BUF_CTL(port);
154 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
643 uint32_t reg, val;
679 reg = WRPLL_CTL1;
685 reg = WRPLL_CTL2;
692 if(I915_READ(reg) & WRPLL_PLL_ENABLE)
706 reg = SPLL_CTL;
713 if(I915_READ(reg) & SPLL_PLL_ENABLE)
724 I915_WRITE(reg, val);
853 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
854 uint32_t val = I915_READ(reg);
858 I915_WRITE(reg, val);