Lines Matching refs:regfile
78 dev_priv->regfile.saveVGA0 = I915_READ(VGA0);
79 dev_priv->regfile.saveVGA1 = I915_READ(VGA1);
80 dev_priv->regfile.saveVGA_PD = I915_READ(VGA_PD);
81 dev_priv->regfile.saveVGACNTRL = I915_READ(i915_vgacntrl_reg(dev));
84 dev_priv->regfile.saveDACMASK = I915_READ8(VGA_DACMASK);
87 dev_priv->regfile.saveMSR = I915_READ8(VGA_MSR_READ);
88 if (dev_priv->regfile.saveMSR & VGA_MSR_CGA_MODE) {
103 dev_priv->regfile.saveCR[i] =
106 dev_priv->regfile.saveCR[0x11] &= ~0x80;
110 dev_priv->regfile.saveAR_INDEX = I915_READ8(VGA_AR_INDEX);
112 dev_priv->regfile.saveAR[i] = i915_read_ar(dev, st01, i, 0);
114 I915_WRITE8(VGA_AR_INDEX, dev_priv->regfile.saveAR_INDEX);
119 dev_priv->regfile.saveGR[i] =
122 dev_priv->regfile.saveGR[0x10] =
124 dev_priv->regfile.saveGR[0x11] =
126 dev_priv->regfile.saveGR[0x18] =
131 dev_priv->regfile.saveSR[i] =
142 I915_WRITE(i915_vgacntrl_reg(dev), dev_priv->regfile.saveVGACNTRL);
144 I915_WRITE(VGA0, dev_priv->regfile.saveVGA0);
145 I915_WRITE(VGA1, dev_priv->regfile.saveVGA1);
146 I915_WRITE(VGA_PD, dev_priv->regfile.saveVGA_PD);
151 I915_WRITE8(VGA_MSR_WRITE, dev_priv->regfile.saveMSR);
152 if (dev_priv->regfile.saveMSR & VGA_MSR_CGA_MODE) {
165 dev_priv->regfile.saveSR[i]);
169 i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->regfile.saveCR[0x11]);
171 i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->regfile.saveCR[i]);
176 dev_priv->regfile.saveGR[i]);
179 dev_priv->regfile.saveGR[0x10]);
181 dev_priv->regfile.saveGR[0x11]);
183 dev_priv->regfile.saveGR[0x18]);
188 i915_write_ar(dev, st01, i, dev_priv->regfile.saveAR[i], 0);
190 I915_WRITE8(VGA_AR_INDEX, dev_priv->regfile.saveAR_INDEX | 0x20);
194 I915_WRITE8(VGA_DACMASK, dev_priv->regfile.saveDACMASK);
204 dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
207 /* Don't regfile.save them in KMS mode */
215 dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
216 dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1);
217 dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2);
218 dev_priv->regfile.saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL);
219 dev_priv->regfile.saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2);
221 dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS);
223 dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
224 dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
225 dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
226 dev_priv->regfile.saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);
228 dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
230 dev_priv->regfile.saveLVDS = I915_READ(LVDS);
236 dev_priv->regfile.savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
239 dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
240 dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
241 dev_priv->regfile.savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);
243 dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
244 dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
245 dev_priv->regfile.savePP_DIVISOR = I915_READ(PP_DIVISOR);
248 /* Only regfile.save FBC state on the platform that supports FBC */
251 dev_priv->regfile.saveDPFC_CB_BASE = I915_READ(ILK_DPFC_CB_BASE);
253 dev_priv->regfile.saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE);
255 dev_priv->regfile.saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
256 dev_priv->regfile.saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
257 dev_priv->regfile.saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
258 dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
274 I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
283 I915_WRITE(BLC_PWM_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
289 I915_WRITE(PCH_LVDS, dev_priv->regfile.saveLVDS & mask);
291 I915_WRITE(LVDS, dev_priv->regfile.saveLVDS & mask);
294 I915_WRITE(PFIT_CONTROL, dev_priv->regfile.savePFIT_CONTROL);
297 I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->regfile.saveBLC_PWM_CTL);
298 I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
302 I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->regfile.saveBLC_CPU_PWM_CTL2);
303 I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->regfile.saveBLC_CPU_PWM_CTL);
304 I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
305 I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
306 I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
307 I915_WRITE(PCH_PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
309 dev_priv->regfile.saveMCHBAR_RENDER_STANDBY);
311 I915_WRITE(PFIT_PGM_RATIOS, dev_priv->regfile.savePFIT_PGM_RATIOS);
312 I915_WRITE(BLC_PWM_CTL, dev_priv->regfile.saveBLC_PWM_CTL);
313 I915_WRITE(BLC_HIST_CTL, dev_priv->regfile.saveBLC_HIST_CTL);
314 I915_WRITE(PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
315 I915_WRITE(PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
316 I915_WRITE(PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
317 I915_WRITE(PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
326 I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->regfile.saveDPFC_CB_BASE);
328 I915_WRITE(DPFC_CB_BASE, dev_priv->regfile.saveDPFC_CB_BASE);
330 I915_WRITE(FBC_CFB_BASE, dev_priv->regfile.saveFBC_CFB_BASE);
331 I915_WRITE(FBC_LL_BASE, dev_priv->regfile.saveFBC_LL_BASE);
332 I915_WRITE(FBC_CONTROL2, dev_priv->regfile.saveFBC_CONTROL2);
333 I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
348 pci_read_config_byte(dev->pdev, LBB, &dev_priv->regfile.saveLBB);
357 dev_priv->regfile.saveDEIER = I915_READ(DEIER);
358 dev_priv->regfile.saveDEIMR = I915_READ(DEIMR);
359 dev_priv->regfile.saveGTIER = I915_READ(GTIER);
360 dev_priv->regfile.saveGTIMR = I915_READ(GTIMR);
361 dev_priv->regfile.saveFDI_RXA_IMR = I915_READ(_FDI_RXA_IMR);
362 dev_priv->regfile.saveFDI_RXB_IMR = I915_READ(_FDI_RXB_IMR);
363 dev_priv->regfile.saveMCHBAR_RENDER_STANDBY =
365 dev_priv->regfile.savePCH_PORT_HOTPLUG = I915_READ(PCH_PORT_HOTPLUG);
367 dev_priv->regfile.saveIER = I915_READ(IER);
368 dev_priv->regfile.saveIMR = I915_READ(IMR);
375 dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
378 dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
382 dev_priv->regfile.saveSWF0[i] = I915_READ(SWF00 + (i << 2));
383 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF10 + (i << 2));
386 dev_priv->regfile.saveSWF2[i] = I915_READ(SWF30 + (i << 2));
398 pci_write_config_byte(dev->pdev, LBB, dev_priv->regfile.saveLBB);
408 I915_WRITE(DEIER, dev_priv->regfile.saveDEIER);
409 I915_WRITE(DEIMR, dev_priv->regfile.saveDEIMR);
410 I915_WRITE(GTIER, dev_priv->regfile.saveGTIER);
411 I915_WRITE(GTIMR, dev_priv->regfile.saveGTIMR);
412 I915_WRITE(_FDI_RXA_IMR, dev_priv->regfile.saveFDI_RXA_IMR);
413 I915_WRITE(_FDI_RXB_IMR, dev_priv->regfile.saveFDI_RXB_IMR);
414 I915_WRITE(PCH_PORT_HOTPLUG, dev_priv->regfile.savePCH_PORT_HOTPLUG);
416 I915_WRITE(IER, dev_priv->regfile.saveIER);
417 I915_WRITE(IMR, dev_priv->regfile.saveIMR);
422 I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 | 0xffff0000);
425 I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000);
428 I915_WRITE(SWF00 + (i << 2), dev_priv->regfile.saveSWF0[i]);
429 I915_WRITE(SWF10 + (i << 2), dev_priv->regfile.saveSWF1[i]);
432 I915_WRITE(SWF30 + (i << 2), dev_priv->regfile.saveSWF2[i]);