Lines Matching refs:write

505 		/* If we're not in the cpu write domain, set ourself into the gtt
506 * write domain and manually flush cachelines (if required). This
825 /* Manually manage the write flush as we may have not yet
829 * the two (read/write) seqno, so if we haved successfully waited,
830 * we know we have passed the last write.
921 /* Having something in the write domain implies it's in the read
1942 * write domains, emitting any outstanding lazy request and retiring and
2201 * precede the update with write to turn off the fence register,
2446 * When mapping objects through the GTT, userspace wants to be able to write
2466 * will need to serialise the write to the associated fence register?
2719 /** Flushes the GTT write domain for the object if it's dirty. */
2726 /* No actual flushing is required for the GTT write domain. Writes
2739 /** Flushes the CPU write domain for the object if it's dirty. */
2754 * Moves a single object to the GTT read, and possibly write domain.
2760 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, int write)
2772 ret = i915_gem_object_wait_rendering(obj, !write);
2785 /* It should now be out of any other write domains, and we can update
2791 if (write) {
2976 /* It should now be out of any other write domains, and we can update
3003 * Moves a single object to the CPU read, and possibly write domain.
3009 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3018 ret = i915_gem_object_wait_rendering(obj, !write);
3034 /* It should now be out of any other write domains, and we can update
3042 if (write) {