Lines Matching defs:pipe
50 int pipe = intel_plane->pipe;
56 sprctl = I915_READ(SPCNTR(pipe, plane));
117 intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size, true);
119 I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
120 I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
130 I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
132 I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
134 I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
135 I915_WRITE(SPCNTR(pipe, plane), sprctl);
136 I915_MODIFY_DISPBASE(SPSURF(pipe, plane), obj->gtt_offset +
138 POSTING_READ(SPSURF(pipe, plane));
147 int pipe = intel_plane->pipe;
150 I915_WRITE(SPCNTR(pipe, plane), I915_READ(SPCNTR(pipe, plane)) &
153 I915_MODIFY_DISPBASE(SPSURF(pipe, plane), 0);
154 POSTING_READ(SPSURF(pipe, plane));
164 int pipe = intel_plane->pipe;
171 I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
172 I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value);
173 I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask);
175 sprctl = I915_READ(SPCNTR(pipe, plane));
179 I915_WRITE(SPCNTR(pipe, plane), sprctl);
181 POSTING_READ(SPKEYMSK(pipe, plane));
193 int pipe = intel_plane->pipe;
197 key->min_value = I915_READ(SPKEYMINVAL(pipe, plane));
198 key->max_value = I915_READ(SPKEYMAXVAL(pipe, plane));
199 key->channel_mask = I915_READ(SPKEYMSK(pipe, plane));
201 sprctl = I915_READ(SPCNTR(pipe, plane));
218 int pipe = intel_plane->pipe;
224 sprctl = I915_READ(SPRCTL(pipe));
271 intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size, true);
279 dev_priv->sprite_scaling_enabled |= 1 << pipe;
283 intel_wait_for_vblank(dev, pipe);
287 dev_priv->sprite_scaling_enabled &= ~(1 << pipe);
289 I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
290 I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
301 I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
303 I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
305 I915_WRITE(SPRLINOFF(pipe), linear_offset);
307 I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
309 I915_WRITE(SPRSCALE(pipe), sprscale);
310 I915_WRITE(SPRCTL(pipe), sprctl);
311 I915_MODIFY_DISPBASE(SPRSURF(pipe), obj->gtt_offset + sprsurf_offset);
312 POSTING_READ(SPRSURF(pipe));
325 int pipe = intel_plane->pipe;
328 I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE);
331 I915_WRITE(SPRSCALE(pipe), 0);
333 I915_MODIFY_DISPBASE(SPRSURF(pipe), 0);
334 POSTING_READ(SPRSURF(pipe));
336 dev_priv->sprite_scaling_enabled &= ~(1 << pipe);
338 intel_update_sprite_watermarks(dev, pipe, 0, 0, false);
357 I915_WRITE(SPRKEYVAL(intel_plane->pipe), key->min_value);
358 I915_WRITE(SPRKEYMAX(intel_plane->pipe), key->max_value);
359 I915_WRITE(SPRKEYMSK(intel_plane->pipe), key->channel_mask);
361 sprctl = I915_READ(SPRCTL(intel_plane->pipe));
367 I915_WRITE(SPRCTL(intel_plane->pipe), sprctl);
369 POSTING_READ(SPRKEYMSK(intel_plane->pipe));
384 key->min_value = I915_READ(SPRKEYVAL(intel_plane->pipe));
385 key->max_value = I915_READ(SPRKEYMAX(intel_plane->pipe));
386 key->channel_mask = I915_READ(SPRKEYMSK(intel_plane->pipe));
389 sprctl = I915_READ(SPRCTL(intel_plane->pipe));
409 int pipe = intel_plane->pipe;
414 dvscntr = I915_READ(DVSCNTR(pipe));
458 intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size, true);
464 I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
465 I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
473 I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
475 I915_WRITE(DVSLINOFF(pipe), linear_offset);
477 I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
478 I915_WRITE(DVSSCALE(pipe), dvsscale);
479 I915_WRITE(DVSCNTR(pipe), dvscntr);
480 I915_MODIFY_DISPBASE(DVSSURF(pipe), obj->gtt_offset + dvssurf_offset);
481 POSTING_READ(DVSSURF(pipe));
490 int pipe = intel_plane->pipe;
492 I915_WRITE(DVSCNTR(pipe), I915_READ(DVSCNTR(pipe)) & ~DVS_ENABLE);
494 I915_WRITE(DVSSCALE(pipe), 0);
496 I915_MODIFY_DISPBASE(DVSSURF(pipe), 0);
497 POSTING_READ(DVSSURF(pipe));
546 I915_WRITE(DVSKEYVAL(intel_plane->pipe), key->min_value);
547 I915_WRITE(DVSKEYMAX(intel_plane->pipe), key->max_value);
548 I915_WRITE(DVSKEYMSK(intel_plane->pipe), key->channel_mask);
550 dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
556 I915_WRITE(DVSCNTR(intel_plane->pipe), dvscntr);
558 POSTING_READ(DVSKEYMSK(intel_plane->pipe));
573 key->min_value = I915_READ(DVSKEYVAL(intel_plane->pipe));
574 key->max_value = I915_READ(DVSKEYMAX(intel_plane->pipe));
575 key->channel_mask = I915_READ(DVSKEYMSK(intel_plane->pipe));
578 dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
615 int pipe = intel_plane->pipe;
617 pipe);
663 /* Don't modify another pipe's plane */
664 if (intel_plane->pipe != intel_crtc->pipe) {
839 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
864 intel_wait_for_vblank(dev, intel_plane->pipe);
1002 intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
1069 intel_plane->pipe = pipe;
1071 possible_crtcs = (1 << pipe);