Cross Reference: /solaris-x11-s11/open-src/kernel/i915/src/intel

Lines Matching refs:flags
219 	u32 flags = 0;
234 		flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
235 		flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
240 		flags |= PIPE_CONTROL_CS_STALL;
243 		flags |= PIPE_CONTROL_TLB_INVALIDATE;
244 		flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
245 		flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
246 		flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
247 		flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
248 		flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
252 		flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
260 	intel_ring_emit(ring, flags);
312 	u32 flags = 0;
325 	flags |= PIPE_CONTROL_CS_STALL;
332 		flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
333 		flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
336 		flags |= PIPE_CONTROL_TLB_INVALIDATE;
337 		flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
338 		flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
339 		flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
340 		flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
341 		flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
345 		flags |= PIPE_CONTROL_QW_WRITE;
346 		flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
359 	intel_ring_emit(ring, flags);
834 	unsigned long flags;
839 	spin_lock_irqsave(&dev_priv->irq_lock, flags);
845 	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
855 	unsigned long flags;
857 	spin_lock_irqsave(&dev_priv->irq_lock, flags);
863 	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
871 	unsigned long flags;
876 	spin_lock_irqsave(&dev_priv->irq_lock, flags);
882 	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
892 	unsigned long flags;
894 	spin_lock_irqsave(&dev_priv->irq_lock, flags);
900 	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
908 	unsigned long flags;
913 	spin_lock_irqsave(&dev_priv->irq_lock, flags);
919 	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
929 	unsigned long flags;
931 	spin_lock_irqsave(&dev_priv->irq_lock, flags);
937 	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1027 	unsigned long flags;
1037 	spin_lock_irqsave(&dev_priv->irq_lock, flags);
1049 	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1059 	unsigned long flags;
1061 	spin_lock_irqsave(&dev_priv->irq_lock, flags);
1072 	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1082 	unsigned long flags;
1087 	spin_lock_irqsave(&dev_priv->rps.lock, flags);
1094 	spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
1104 	unsigned long flags;
1109 	spin_lock_irqsave(&dev_priv->rps.lock, flags);
1116 	spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
1122 			unsigned flags)
1133 			(flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1145 				unsigned flags)
1149 	if (flags & I915_DISPATCH_PINNED) {
1155 		intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1186 		intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1197 			unsigned flags)
1206 	intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1332 	ring->map.flags = 0;
1697 			      unsigned flags)
1707 			(flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW));
1718 				unsigned flags)
1728 			(flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1918 	ring->map.flags = 0;