Lines Matching defs:flush
147 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
173 * The cache flushes require the workaround flush that triggered this
229 /* Just flush everything. Experiments have shown that reducing the
327 /* Just flush everything. Experiments have shown that reducing the
1540 /* We need to add any requests required to flush the objects and ring */
1667 u32 invalidate, u32 flush)
1679 * "If ENABLED, all TLBs will be invalidated once the flush
1739 u32 invalidate, u32 flush)
1752 * "If ENABLED, all TLBs will be invalidated once the flush
1765 if (IS_GEN7(dev) && flush)
1782 ring->flush = gen7_render_ring_flush;
1784 ring->flush = gen6_render_ring_flush;
1801 ring->flush = gen4_render_ring_flush;
1811 ring->flush = gen2_render_ring_flush;
1813 ring->flush = gen4_render_ring_flush;
1883 ring->flush = gen2_render_ring_flush;
1885 ring->flush = gen4_render_ring_flush;
1953 ring->flush = gen6_bsd_ring_flush;
1972 ring->flush = bsd_ring_flush;
2002 ring->flush = gen6_ring_flush;
2034 ring->flush = gen6_ring_flush;
2065 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2084 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);