Lines Matching refs:reg
1098 u32 reg;
1118 reg = I915_READ(DSPFW1);
1119 reg &= ~DSPFW_SR_MASK;
1120 reg |= wm << DSPFW_SR_SHIFT;
1121 I915_WRITE(DSPFW1, reg);
1122 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1128 reg = I915_READ(DSPFW3);
1129 reg &= ~DSPFW_CURSOR_SR_MASK;
1130 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1131 I915_WRITE(DSPFW3, reg);
1137 reg = I915_READ(DSPFW3);
1138 reg &= ~DSPFW_HPLL_SR_MASK;
1139 reg |= wm & DSPFW_HPLL_SR_MASK;
1140 I915_WRITE(DSPFW3, reg);
1146 reg = I915_READ(DSPFW3);
1147 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1148 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1149 I915_WRITE(DSPFW3, reg);
1150 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2738 int sprite_wm, reg;
2746 reg = WM0_PIPEA_ILK;
2749 reg = WM0_PIPEB_ILK;
2752 reg = WM0_PIPEC_IVB;
2767 val = I915_READ(reg);
2769 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
4144 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
4146 reg &= ~GEN7_FF_SCHED_MASK;
4147 reg |= GEN7_FF_TS_SCHED_HW;
4148 reg |= GEN7_FF_VS_SCHED_HW;
4149 reg |= GEN7_FF_DS_SCHED_HW;
4152 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
4154 I915_WRITE(GEN7_FF_THREAD_MODE, reg);