Lines Matching refs:ips
686 dev_priv->ips.r_t = dev_priv->mem_freq;
718 dev_priv->ips.c_m = 0;
720 dev_priv->ips.c_m = 1;
722 dev_priv->ips.c_m = 2;
2964 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2965 dev_priv->ips.fstart = fstart;
2967 dev_priv->ips.max_delay = fstart;
2968 dev_priv->ips.min_delay = fmin;
2969 dev_priv->ips.cur_delay = fstart;
2992 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2994 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2995 dev_priv->ips.last_count2 = I915_READ(0x112f4);
2996 dev_priv->ips.last_time2 = jiffies;
3018 (void) ironlake_set_drps(dev, dev_priv->ips.fstart);
3633 if (dev_priv->ips.renderctx) {
3634 i915_gem_object_unpin(dev_priv->ips.renderctx);
3635 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
3636 dev_priv->ips.renderctx = NULL;
3639 if (dev_priv->ips.pwrctx) {
3640 i915_gem_object_unpin(dev_priv->ips.pwrctx);
3641 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
3642 dev_priv->ips.pwrctx = NULL;
3668 if (dev_priv->ips.renderctx == NULL)
3669 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
3670 if (!dev_priv->ips.renderctx)
3673 if (dev_priv->ips.pwrctx == NULL)
3674 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
3675 if (!dev_priv->ips.pwrctx) {
3718 intel_ring_emit(ring, dev_priv->ips.renderctx->gtt_offset |
3741 I915_WRITE(PWRCTXA, dev_priv->ips.pwrctx->gtt_offset | PWRCTX_EN);
3842 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);