Lines Matching refs:enabled
46 * FBC-related functionality can be enabled by the means of the
119 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
154 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
234 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
309 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1080 struct drm_crtc *crtc, *enabled = NULL;
1084 if (enabled)
1086 enabled = crtc;
1090 return enabled;
1155 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1378 unsigned int enabled = 0;
1386 enabled |= 1 << PIPE_A;
1392 enabled |= 1 << PIPE_B;
1394 if (single_plane_enabled(enabled) &&
1395 g4x_compute_srwm(dev, ffs(enabled) - 1,
1400 g4x_compute_srwm(dev, ffs(enabled) - 1,
1436 unsigned int enabled = 0;
1442 enabled |= 1 << PIPE_A;
1448 enabled |= 1 << PIPE_B;
1450 if (single_plane_enabled(enabled) &&
1451 g4x_compute_srwm(dev, ffs(enabled) - 1,
1530 /* Turn off self refresh if both pipes are enabled */
1556 struct drm_crtc *crtc, *enabled = NULL;
1575 enabled = crtc;
1589 if (enabled == NULL)
1590 enabled = crtc;
1592 enabled = NULL;
1610 if (HAS_FW_BLC(dev) && enabled) {
1613 int clock = enabled->mode.clock;
1614 int htotal = enabled->mode.htotal;
1615 int hdisplay = enabled->mode.hdisplay;
1616 int pixel_size = enabled->fb->bits_per_pixel / 8;
1652 if (enabled) {
1658 DRM_DEBUG_KMS("memory self refresh enabled\n");
1798 unsigned int enabled;
1800 enabled = 0;
1812 enabled |= 1 << PIPE_A;
1826 enabled |= 1 << PIPE_B;
1837 if (!single_plane_enabled(enabled))
1839 enabled = ffs(enabled) - 1;
1842 if (!ironlake_compute_srwm(dev, 1, enabled,
1857 if (!ironlake_compute_srwm(dev, 2, enabled,
1883 unsigned int enabled;
1885 enabled = 0;
1897 enabled |= 1 << PIPE_A;
1911 enabled |= 1 << PIPE_B;
1920 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1928 if (!single_plane_enabled(enabled) ||
1931 enabled = ffs(enabled) - 1;
1934 if (!ironlake_compute_srwm(dev, 1, enabled,
1949 if (!ironlake_compute_srwm(dev, 2, enabled,
1964 if (!ironlake_compute_srwm(dev, 3, enabled,
1986 unsigned int enabled;
1988 enabled = 0;
2000 enabled |= 1 << PIPE_A;
2014 enabled |= 1 << PIPE_B;
2028 enabled |= 1 << PIPE_C;
2037 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
2045 if (!single_plane_enabled(enabled) ||
2048 enabled = ffs(enabled) - 1;
2051 if (!ironlake_compute_srwm(dev, 1, enabled,
2066 if (!ironlake_compute_srwm(dev, 2, enabled,
2081 if (!ironlake_compute_srwm(dev, 3, enabled,
2086 !ironlake_compute_srwm(dev, 3, enabled,
2210 /* TODO: for now, assume the primary plane is always enabled. */
2486 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2977 * Interrupts will be enabled in ironlake_irq_postinstall
3211 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
3343 /* requires MSI enabled */
3580 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
3617 /* requires MSI enabled */
4162 * TODO: this bit should only be enabled when really needed, then
4522 * enable it, so check if it's enabled and also check if we've requested it to
4523 * be enabled.
4673 * to be enabled, and it will only be disabled if none of the registers is
4674 * requesting it to be enabled.
4683 /* For now, we need the power well to be always enabled. */
5017 /* BIOS often leaves RC6 enabled, but disable it for hw init */