Lines Matching refs:display
316 if (!dev_priv->display.fbc_enabled)
319 return dev_priv->display.fbc_enabled(dev);
335 dev_priv->display.enable_fbc(work->crtc,
389 if (!dev_priv->display.enable_fbc)
396 dev_priv->display.enable_fbc(crtc, interval);
414 * display to settle before starting the compression. Note that
433 if (!dev_priv->display.disable_fbc)
436 dev_priv->display.disable_fbc(dev);
805 * FIFO underruns and display "flicker").
1032 * @pixel_size: display pixel size
1035 * Calculate the watermark level (the level at which the display plane will
1036 * start fetching from memory again). Each chip has a different display
1044 * will occur, and a display engine hang could result.
1164 const struct intel_watermark_params *display,
1179 *plane_wm = display->guard_size;
1190 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1193 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1194 *plane_wm = entries + display->guard_size;
1195 if (*plane_wm > (int)display->max_wm)
1196 *plane_wm = display->max_wm;
1222 const struct intel_watermark_params *display,
1225 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1228 if (display_wm > display->max_wm) {
1229 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1230 display_wm, display->max_wm);
1251 const struct intel_watermark_params *display,
1281 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1282 *display_wm = entries + display->guard_size;
1284 /* calculate the self-refresh watermark for display cursor */
1291 display, cursor);
1524 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1565 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1579 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1676 dev_priv->display.get_fifo_size(dev, 0),
1698 const struct intel_watermark_params *display,
1703 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1720 if (display_wm > display->max_wm) {
1721 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1745 const struct intel_watermark_params *display,
1775 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1776 *display_wm = entries + display->guard_size;
1784 /* calculate the self-refresh watermark for display cursor */
1791 display, cursor);
1831 * display plane is used.
1916 * display plane is used.
2033 * display plane is used.
2658 const struct intel_watermark_params *display,
2667 *sprite_wm = display->guard_size;
2675 tlb_miss = display->fifo_size*display->cacheline_size -
2679 entries = DIV_ROUND_UP(entries, display->cacheline_size);
2680 *sprite_wm = entries + display->guard_size;
2681 if (*sprite_wm > (int)display->max_wm)
2682 *sprite_wm = display->max_wm;
2690 const struct intel_watermark_params *display,
2725 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
2726 *sprite_wm = entries + display->guard_size;
2850 if (dev_priv->display.update_wm)
2851 dev_priv->display.update_wm(dev);
2860 if (dev_priv->display.update_sprite_wm)
2861 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
4018 /* The below fixes the weird display corruption, a few pixels shifted
4047 DRM_INFO("This can cause pipe underruns and display issues.\n");
4511 dev_priv->display.init_clock_gating(dev);
4699 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
4701 dev_priv->display.enable_fbc =
4704 dev_priv->display.enable_fbc =
4706 dev_priv->display.disable_fbc = ironlake_disable_fbc;
4708 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4709 dev_priv->display.enable_fbc = g4x_enable_fbc;
4710 dev_priv->display.disable_fbc = g4x_disable_fbc;
4712 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4713 dev_priv->display.enable_fbc = i8xx_enable_fbc;
4714 dev_priv->display.disable_fbc = i8xx_disable_fbc;
4729 dev_priv->display.update_wm = ironlake_update_wm;
4733 dev_priv->display.update_wm = NULL;
4735 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
4738 dev_priv->display.update_wm = sandybridge_update_wm;
4739 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4741 DRM_DEBUG_KMS("Failed to read display plane latency. "
4743 dev_priv->display.update_wm = NULL;
4745 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
4749 dev_priv->display.update_wm = ivybridge_update_wm;
4750 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4752 DRM_DEBUG_KMS("Failed to read display plane latency. "
4754 dev_priv->display.update_wm = NULL;
4756 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
4759 dev_priv->display.update_wm = haswell_update_wm;
4760 dev_priv->display.update_sprite_wm =
4763 DRM_DEBUG_KMS("Failed to read display plane latency. "
4765 dev_priv->display.update_wm = NULL;
4767 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
4769 dev_priv->display.update_wm = NULL;
4771 dev_priv->display.update_wm = valleyview_update_wm;
4772 dev_priv->display.init_clock_gating =
4786 dev_priv->display.update_wm = NULL;
4788 dev_priv->display.update_wm = pineview_update_wm;
4789 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
4791 dev_priv->display.update_wm = g4x_update_wm;
4792 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
4794 dev_priv->display.update_wm = i965_update_wm;
4796 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
4798 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
4800 dev_priv->display.update_wm = i9xx_update_wm;
4801 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4802 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
4804 dev_priv->display.update_wm = i830_update_wm;
4805 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
4806 dev_priv->display.get_fifo_size = i830_get_fifo_size;
4808 dev_priv->display.update_wm = i9xx_update_wm;
4809 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4810 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
4812 dev_priv->display.update_wm = i830_update_wm;
4813 dev_priv->display.init_clock_gating = i830_init_clock_gating;
4815 dev_priv->display.get_fifo_size = i845_get_fifo_size;
4817 dev_priv->display.get_fifo_size = i830_get_fifo_size;