Lines Matching defs:plane
89 int plane, i;
98 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
106 fbc_ctl2 |= plane;
119 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
120 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
138 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
142 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
154 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
207 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
213 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
234 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
284 intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
309 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
338 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
446 * - plane A only (on pre-965)
542 intel_crtc->plane != 0) {
543 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
574 if (dev_priv->cfb_plane == intel_crtc->plane &&
812 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
819 if (plane)
823 plane ? "B" : "A", size);
828 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
835 if (plane)
840 plane ? "B" : "A", size);
845 static int i845_get_fifo_size(struct drm_device *dev, int plane)
855 plane ? "B" : "A",
861 static int i830_get_fifo_size(struct drm_device *dev, int plane)
871 plane ? "B" : "A", size);
1035 * Calculate the watermark level (the level at which the display plane will
1163 int plane,
1176 crtc = intel_get_crtc_for_plane(dev, plane);
1188 /* Use the small buffer method to calculate plane watermark */
1225 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1249 int plane,
1267 crtc = intel_get_crtc_for_plane(dev, plane);
1295 int plane,
1305 crtc = intel_get_crtc_for_plane(dev, plane);
1330 * to be programmed. Each plane has a drain latency multiplier and a drain
1342 /* For plane A, Cursor A */
1355 /* For plane B, Cursor B */
1412 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1463 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1489 /* Calc sr entries for one plane configs */
1524 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1609 /* Calc sr entries for one plane configs */
1703 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1743 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1761 crtc = intel_get_crtc_for_plane(dev, plane);
1810 " plane %d, " "cursor: %d\n",
1824 " plane %d, cursor: %d\n",
1831 * display plane is used.
1895 " plane %d, " "cursor: %d\n",
1909 " plane %d, cursor: %d\n",
1916 * display plane is used.
1998 " plane %d, " "cursor: %d\n",
2012 " plane %d, cursor: %d\n",
2026 " plane %d, cursor: %d\n",
2033 * display plane is used.
2210 /* TODO: for now, assume the primary plane is always enabled. */
2366 struct drm_plane *plane;
2402 list_for_each_entry(plane, struct drm_plane, &dev->mode_config.plane_list, head) {
2403 struct intel_plane *intel_plane = to_intel_plane(plane);
2639 struct drm_plane *plane;
2641 list_for_each_entry(plane, struct drm_plane, &dev->mode_config.plane_list, head) {
2642 struct intel_plane *intel_plane = to_intel_plane(plane);
2656 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2665 crtc = intel_get_crtc_for_plane(dev, plane);
2688 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
2705 crtc = intel_get_crtc_for_plane(dev, plane);
2818 * and plane configuration.
2837 * surface width = hdisplay for normal plane and 64 for cursor
4741 DRM_DEBUG_KMS("Failed to read display plane latency. "
4752 DRM_DEBUG_KMS("Failed to read display plane latency. "
4763 DRM_DEBUG_KMS("Failed to read display plane latency. "