Lines Matching defs:pipe

295 		I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
480 	 *   - more than one pipe is active
489 				DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
599 		 * disabling the FBC. However, along all current pipe
1809 		DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1823 		DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1894 		DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1908 		DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1997 		DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
2011 		DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
2025 		DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
2281 	enum pipe pipe;
2284 	for (pipe = PIPE_A; pipe <= PIPE_C; pipe++) {
2285 		struct hsw_pipe_wm_parameters *p = &params[pipe];
2287 		pri_val[pipe] = hsw_compute_pri_wm(p, mem_value, true);
2288 		spr_val[pipe] = hsw_compute_spr_wm(p, mem_value);
2289 		cur_val[pipe] = hsw_compute_cur_wm(p, mem_value);
2290 		fbc_val[pipe] = hsw_compute_fbc_wm(p, pri_val[pipe], mem_value);
2312 				    uint32_t mem_value, enum pipe pipe,
2322 	     DRM_ERROR("Primary WM error, mode not supported for pipe %c\n",
2323 	     pipe_name(pipe));
2325 	     DRM_ERROR("Sprite WM error, mode not supported for pipe %c\n",
2326 	     pipe_name(pipe));
2328 	     DRM_ERROR("Cursor WM error, mode not supported for pipe %c\n",
2329 	     pipe_name(pipe));
2368 	enum pipe pipe;
2384 		pipe = intel_crtc->pipe;
2385 		p = &params[pipe];
2406 		pipe = intel_plane->pipe;
2407 		p = &params[pipe];
2440 	enum pipe pipe;
2475 	for_each_pipe(pipe)
2476 		results->wm_pipe[pipe] = hsw_compute_wm_pipe(dev_priv, wm[0],
2477 							     pipe,
2478 							     &params[pipe]);
2480 	for_each_pipe(pipe) {
2481 		crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2482 		results->wm_linetime[pipe] = hsw_compute_linetime_wm(dev, crtc);
2635 static void haswell_update_sprite_wm(struct drm_device *dev, int pipe,
2644 		if (intel_plane->pipe == pipe) {
2731 static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
2744 	switch (pipe) {
2755 		return; /* bad pipe */
2758 	ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
2762 		DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
2763 			      pipe_name(pipe));
2770 	DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
2773 	ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2779 		DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
2780 			      pipe_name(pipe));
2789 	ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2795 		DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
2796 			      pipe_name(pipe));
2801 	ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2807 		DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
2808 			      pipe_name(pipe));
2854 void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
2861 		dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
3926 	int pipe;
3928 	for_each_pipe(pipe) {
3929 		I915_WRITE(DSPCNTR(pipe),
3930 			   I915_READ(DSPCNTR(pipe)) |
3932 		intel_flush_display_plane(dev_priv, pipe);
4007 	int pipe;
4021 	for_each_pipe(pipe) {
4022 		val = I915_READ(TRANS_CHICKEN2(pipe));
4030 		I915_WRITE(TRANS_CHICKEN2(pipe), val);
4033 	for_each_pipe(pipe) {
4034 		I915_WRITE(TRANS_CHICKEN1(pipe),
4047 		DRM_INFO("This can cause pipe underruns and display issues.\n");
4576 			enum pipe p;