Lines Matching defs:latency
769 const struct cxsr_latency *latency;
776 latency = &cxsr_latency_table[i];
777 if (is_desktop == latency->is_desktop &&
778 is_ddr3 == latency->is_ddr3 &&
779 fsb == latency->fsb_freq && mem == latency->mem_freq)
780 return latency;
808 * platforms but not overly aggressive on lower latency configs.
1033 * @latency_ns: memory latency for the platform
1056 * latency values.
1058 * latency is usually a few thousand
1097 const struct cxsr_latency *latency;
1101 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1103 if (!latency) {
1117 pixel_size, latency->display_sr);
1127 pixel_size, latency->cursor_sr);
1136 pixel_size, latency->display_hpll_disable);
1145 pixel_size, latency->cursor_hpll_disable);
1241 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1327 * Update drain latency registers of memory arbiter
1329 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1330 * to be programmed. Each plane has a drain latency multiplier and a drain
1331 * latency value.
1492 /* self-refresh has much higher latency */
1611 /* self-refresh has much higher latency */
1733 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1872 * WM3 is unsupported on ILK, probably because we don't have latency
1880 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1887 &sandybridge_display_wm_info, latency,
1888 &sandybridge_cursor_wm_info, latency,
1901 &sandybridge_display_wm_info, latency,
1902 &sandybridge_cursor_wm_info, latency,
1982 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1990 &sandybridge_display_wm_info, latency,
1991 &sandybridge_cursor_wm_info, latency,
2004 &sandybridge_display_wm_info, latency,
2005 &sandybridge_cursor_wm_info, latency,
2018 &sandybridge_display_wm_info, latency,
2019 &sandybridge_cursor_wm_info, latency,
2080 /* WM3, note we have to correct the cursor latency */
2133 uint32_t latency)
2137 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
2145 uint32_t latency)
2149 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
2736 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
2760 latency, &sprite_wm);
2825 * lines), so need to account for TLB latency
2828 * watermark = dotclock * bytes per pixel * latency
2829 * where latency is platform & configuration dependent (we assume pessimal
2833 * watermark = (trunc(latency/line time)+1) * surface width *
2838 * and latency is assumed to be high, as above.
4731 DRM_DEBUG_KMS("Failed to get proper latency. "
4741 DRM_DEBUG_KMS("Failed to read display plane latency. "
4752 DRM_DEBUG_KMS("Failed to read display plane latency. "
4763 DRM_DEBUG_KMS("Failed to read display plane latency. "
4779 DRM_INFO("failed to find known CxSR latency "