Cross Reference: /solaris-x11-s11/open-src/kernel/i915/src/intel

Lines Matching defs:crtc
50 static bool intel_crtc_active(struct drm_crtc *crtc)
55 	return to_intel_crtc(crtc)->active && crtc->fb && crtc->mode.clock;
80 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
82 	struct drm_device *dev = crtc->dev;
84 	struct drm_framebuffer *fb = crtc->fb;
87 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
108 	I915_WRITE(FBC_FENCE_OFF, crtc->y);
120 		      cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
130 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
132 	struct drm_device *dev = crtc->dev;
134 	struct drm_framebuffer *fb = crtc->fb;
137 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
149 	I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
199 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
201 	struct drm_device *dev = crtc->dev;
203 	struct drm_framebuffer *fb = crtc->fb;
206 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
222 	I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
230 		I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
271 static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
273 	struct drm_device *dev = crtc->dev;
275 	struct drm_framebuffer *fb = crtc->fb;
278 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
305 	I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
334 		if (work->crtc->fb == work->fb) {
335 			dev_priv->display.enable_fbc(work->crtc,
338 			dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
339 			dev_priv->cfb_fb = work->crtc->fb->base.id;
340 			dev_priv->cfb_y = work->crtc->y;
383 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
386 	struct drm_device *dev = crtc->dev;
396 		dev_priv->display.enable_fbc(crtc, interval);
400 	work->dev =  crtc->dev;
401 	work->crtc = crtc;
402 	work->fb = crtc->fb;
462 	struct drm_crtc *crtc = NULL, *tmp_crtc;
488 			if (crtc) {
493 			crtc = tmp_crtc;
497 	if (!crtc || crtc->fb == NULL) {
503 	intel_crtc = to_intel_crtc(crtc);
504 	fb = crtc->fb;
520 	if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
521 	    (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
535 	if ((crtc->mode.hdisplay > max_hdisplay) ||
536 	    (crtc->mode.vdisplay > max_vdisplay)) {
576 	    dev_priv->cfb_y == crtc->y)
580 		/* We update FBC along two paths, after changing fb/crtc
607 	intel_enable_fbc(crtc, 500);
1080 	struct drm_crtc *crtc, *enabled = NULL;
1082 	list_for_each_entry(crtc, struct drm_crtc, &dev->mode_config.crtc_list, head) {
1083 		if (intel_crtc_active(crtc)) {
1086 			enabled = crtc;
1096 	struct drm_crtc *crtc;
1109 	crtc = single_enabled_crtc(dev);
1110 	if (crtc) {
1111 		int clock = crtc->mode.clock;
1112 		int pixel_size = crtc->fb->bits_per_pixel / 8;
1171 	struct drm_crtc *crtc;
1176 	crtc = intel_get_crtc_for_plane(dev, plane);
1177 	if (!intel_crtc_active(crtc)) {
1183 	htotal = crtc->mode.htotal;
1184 	hdisplay = crtc->mode.hdisplay;
1185 	clock = crtc->mode.clock;
1186 	pixel_size = crtc->fb->bits_per_pixel / 8;
1255 	struct drm_crtc *crtc;
1267 	crtc = intel_get_crtc_for_plane(dev, plane);
1268 	hdisplay = crtc->mode.hdisplay;
1269 	htotal = crtc->mode.htotal;
1270 	clock = crtc->mode.clock;
1271 	pixel_size = crtc->fb->bits_per_pixel / 8;
1301 	struct drm_crtc *crtc;
1305 	crtc = intel_get_crtc_for_plane(dev, plane);
1306 	if (!intel_crtc_active(crtc))
1309 	clock = crtc->mode.clock;	/* VESA DOT Clock */
1310 	pixel_size = crtc->fb->bits_per_pixel / 8;	/* BPP */
1485 	struct drm_crtc *crtc;
1490 	crtc = single_enabled_crtc(dev);
1491 	if (crtc) {
1494 		int clock = crtc->mode.clock;
1495 		int htotal = crtc->mode.htotal;
1496 		int hdisplay = crtc->mode.hdisplay;
1497 		int pixel_size = crtc->fb->bits_per_pixel / 8;
1556 	struct drm_crtc *crtc, *enabled = NULL;
1566 	crtc = intel_get_crtc_for_plane(dev, 0);
1567 	if (intel_crtc_active(crtc)) {
1568 		int cpp = crtc->fb->bits_per_pixel / 8;
1572 		planea_wm = intel_calculate_wm(crtc->mode.clock,
1575 		enabled = crtc;
1580 	crtc = intel_get_crtc_for_plane(dev, 1);
1581 	if (intel_crtc_active(crtc)) {
1582 		int cpp = crtc->fb->bits_per_pixel / 8;
1586 		planeb_wm = intel_calculate_wm(crtc->mode.clock,
1590 			enabled = crtc;
1667 	struct drm_crtc *crtc;
1671 	crtc = single_enabled_crtc(dev);
1672 	if (crtc == NULL)
1675 	planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
1749 	struct drm_crtc *crtc;
1761 	crtc = intel_get_crtc_for_plane(dev, plane);
1762 	hdisplay = crtc->mode.hdisplay;
1763 	htotal = crtc->mode.htotal;
1764 	clock = crtc->mode.clock;
1765 	pixel_size = crtc->fb->bits_per_pixel / 8;
2102 				      struct drm_crtc *crtc)
2104 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2337 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2340 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2344 	if (!intel_crtc_active(crtc))
2365 	struct drm_crtc *crtc;
2380 	list_for_each_entry(crtc, struct drm_crtc, &dev->mode_config.crtc_list, head) {
2381 		struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2387 		p->active = intel_crtc_active(crtc);
2394 		p->pixel_rate = hsw_wm_get_pixel_rate(dev, crtc);
2395 		p->pri_bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
2438 	struct drm_crtc *crtc;
2481 		crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2482 		results->wm_linetime[pipe] = hsw_compute_linetime_wm(dev, crtc);
2661 	struct drm_crtc *crtc;
2665 	crtc = intel_get_crtc_for_plane(dev, plane);
2666 	if (!intel_crtc_active(crtc)) {
2671 	clock = crtc->mode.clock;
2693 	struct drm_crtc *crtc;
2705 	crtc = intel_get_crtc_for_plane(dev, plane);
2706 	clock = crtc->mode.clock;