Lines Matching refs:gmbus
208 /* -1 to map pin pair to gmbus index */
229 * gmbus on gen4 seems to be able to generate legacy interrupts even when in MSI
364 * The gmbus controller can combine a 1 or 2 byte write with a read that
449 /* Generate a STOP condition on the bus. Note that gmbus can't generata
451 * unconditionally generate the STOP condition with an additional gmbus
478 * from retrying. So return -ENXIO only when gmbus properly quiescents -
549 struct intel_gmbus *bus = &dev_priv->gmbus[i];
550 u32 port = i + 1; /* +1 to map gmbus index to pin pair */
554 "i915 gmbus %s",
565 /* gmbus seems to be broken on i830 */
581 /* -1 to map pin pair to gmbus index */
583 &dev_priv->gmbus[port - 1].adapter : NULL;
607 struct intel_gmbus *bus = &dev_priv->gmbus[i];