Cross Reference: /solaris-x11-s11/open-src/kernel/i915/src/intel

Lines Matching defs:dev_priv
68 	struct drm_i915_private *dev_priv = dev->dev_private;
69 	I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0);
72 static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
77 	if (!IS_PINEVIEW(dev_priv->dev))
90 	struct drm_i915_private *dev_priv = bus->dev_priv;
91 	struct drm_device *dev = dev_priv->dev;
106 	struct drm_i915_private *dev_priv = bus->dev_priv;
113 	struct drm_i915_private *dev_priv = bus->dev_priv;
120 	struct drm_i915_private *dev_priv = bus->dev_priv;
130 	struct drm_i915_private *dev_priv = bus->dev_priv;
140 	struct drm_i915_private *dev_priv = bus->dev_priv;
157 	struct drm_i915_private *dev_priv = bus->dev_priv;
177 	struct drm_i915_private *dev_priv = bus->dev_priv;
179 	intel_i2c_reset(dev_priv->dev);
180 	intel_i2c_quirk_set(dev_priv, true);
193 	struct drm_i915_private *dev_priv = bus->dev_priv;
197 	intel_i2c_quirk_set(dev_priv, false);
203 	struct drm_i915_private *dev_priv = bus->dev_priv;
209 	bus->gpio_reg = dev_priv->gpio_mmio_base + gmbus_ports[pin - 1].reg;
236 gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
240 	int reg_offset = dev_priv->gpio_mmio_base;
243 	if (!HAS_GMBUS_IRQ(dev_priv->dev))
268 gmbus_wait_idle(struct drm_i915_private *dev_priv)
271 	int reg_offset = dev_priv->gpio_mmio_base;
275 	if (!HAS_GMBUS_IRQ(dev_priv->dev))
293 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
296 	int reg_offset = dev_priv->gpio_mmio_base;
310 		ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY,
326 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg)
328 	int reg_offset = dev_priv->gpio_mmio_base;
355 		ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY,
376 gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
378 	int reg_offset = dev_priv->gpio_mmio_base;
394 	ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
411 	struct drm_i915_private *dev_priv = bus->dev_priv;
415 	mutex_lock(&dev_priv->gmbus_mutex);
422 	reg_offset = dev_priv->gpio_mmio_base;
428 			ret = gmbus_xfer_index_read(dev_priv, &msgs[i]);
431 			ret = gmbus_xfer_read(dev_priv, &msgs[i], 0);
433 			ret = gmbus_xfer_write(dev_priv, &msgs[i]);
441 		ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_WAIT_PHASE,
459 	if (gmbus_wait_idle(dev_priv)) {
483 	if (gmbus_wait_idle(dev_priv)) {
513 	mutex_unlock(&dev_priv->gmbus_mutex);
533 	struct drm_i915_private *dev_priv = dev->dev_private;
539 		dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;
541 		dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
543 		dev_priv->gpio_mmio_base = 0;
545 	mutex_init(&dev_priv->gmbus_mutex, NULL, MUTEX_DRIVER, NULL);
546 	DRM_INIT_WAITQUEUE(&dev_priv->gmbus_wait_queue, DRM_INTR_PRI(dev));
549 		struct intel_gmbus *bus = &dev_priv->gmbus[i];
558 		bus->dev_priv = dev_priv;
572 	intel_i2c_reset(dev_priv->dev);
577 struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
583 		&dev_priv->gmbus[port - 1].adapter : NULL;
607 		struct intel_gmbus *bus = &dev_priv->gmbus[i];