Cross Reference: /solaris-x11-s11/open-src/kernel/i915/src/intel

Lines Matching refs:train_set
1632 	uint8_t train_set = intel_dp->train_set[0];
1635 	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1638 		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1661 		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1680 		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1695 		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1748 		intel_dp->train_set[lane] = v | p;
1752 intel_gen4_signal_levels(uint8_t train_set)
1756 	switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1771 	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1791 intel_gen6_edp_signal_levels(uint8_t train_set)
1793 	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1819 intel_gen7_edp_signal_levels(uint8_t train_set)
1821 	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1850 intel_hsw_signal_levels(uint8_t train_set)
1852 	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1890 	uint8_t train_set = intel_dp->train_set[0];
1893 		signal_levels = intel_hsw_signal_levels(train_set);
1899 		signal_levels = intel_gen7_edp_signal_levels(train_set);
1902 		signal_levels = intel_gen6_edp_signal_levels(train_set);
1905 		signal_levels = intel_gen4_signal_levels(train_set);
2001 						intel_dp->train_set,
2064 	memset(intel_dp->train_set, 0, 4);
2070 		/* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
2095 			if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2103 			memset(intel_dp->train_set, 0, 4);
2109 		if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2117 		voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2119 		/* Compute new train_set as requested by target */
2179 		/* Compute new train_set as requested by target */