Cross Reference: /solaris-x11-s11/open-src/kernel/i915/src/intel

Lines Matching refs:pp_ctrl_reg
234 	u32 pp_ctrl_reg;
236 	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
237 	return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
245 	u32 pp_stat_reg, pp_ctrl_reg;
251 	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
257 				I915_READ(pp_ctrl_reg));
922 	u32 pp_stat_reg, pp_ctrl_reg;
925 	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
930 			I915_READ(pp_ctrl_reg));
935 				I915_READ(pp_ctrl_reg));
967 	u32 pp_ctrl_reg;
969 	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
970 	control = I915_READ(pp_ctrl_reg);
982 	u32 pp_stat_reg, pp_ctrl_reg;
1005 	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1007 	I915_WRITE(pp_ctrl_reg, pp);
1008 	POSTING_READ(pp_ctrl_reg);
1010 			I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1025 	u32 pp_stat_reg, pp_ctrl_reg;
1035 		pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1037 		I915_WRITE(pp_ctrl_reg, pp);
1038 		POSTING_READ(pp_ctrl_reg);
1042 		I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1086 	u32 pp_ctrl_reg;
1112 	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1114 	I915_WRITE(pp_ctrl_reg, pp);
1115 	POSTING_READ(pp_ctrl_reg);
1131 	u32 pp_ctrl_reg;
1144 	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1146 	I915_WRITE(pp_ctrl_reg, pp);
1147 	POSTING_READ(pp_ctrl_reg);
1161 	u32 pp_ctrl_reg;
1177 	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1179 	I915_WRITE(pp_ctrl_reg, pp);
1180 	POSTING_READ(pp_ctrl_reg);
1190 	u32 pp_ctrl_reg;
1201 	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1203 	I915_WRITE(pp_ctrl_reg, pp);
1204 	POSTING_READ(pp_ctrl_reg);