Lines Matching refs:pp
981 u32 pp;
1001 pp = ironlake_get_pp_control(intel_dp);
1002 pp |= EDP_FORCE_VDD;
1007 I915_WRITE(pp_ctrl_reg, pp);
1024 u32 pp;
1031 pp = ironlake_get_pp_control(intel_dp);
1032 pp &= ~EDP_FORCE_VDD;
1037 I915_WRITE(pp_ctrl_reg, pp);
1085 u32 pp;
1100 pp = ironlake_get_pp_control(intel_dp);
1103 pp &= ~PANEL_POWER_RESET;
1104 I915_WRITE(PCH_PP_CONTROL, pp);
1108 pp |= POWER_TARGET_ON;
1110 pp |= PANEL_POWER_RESET;
1114 I915_WRITE(pp_ctrl_reg, pp);
1120 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1121 I915_WRITE(PCH_PP_CONTROL, pp);
1130 u32 pp;
1141 pp = ironlake_get_pp_control(intel_dp);
1142 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1146 I915_WRITE(pp_ctrl_reg, pp);
1160 u32 pp;
1174 pp = ironlake_get_pp_control(intel_dp);
1175 pp |= EDP_BLC_ENABLE;
1179 I915_WRITE(pp_ctrl_reg, pp);
1189 u32 pp;
1198 pp = ironlake_get_pp_control(intel_dp);
1199 pp &= ~EDP_BLC_ENABLE;
1203 I915_WRITE(pp_ctrl_reg, pp);
2853 u32 pp_on, pp_off, pp_div, pp;
2870 pp = ironlake_get_pp_control(intel_dp);
2871 I915_WRITE(pp_control_reg, pp);
2969 /* Compute the divisor for the pp clock, simply match the Bspec