Lines Matching refs:IS_VALLEYVIEW

194 	if (IS_VALLEYVIEW(dev))
226 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
236 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
250 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
251 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
299 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
314 if (IS_VALLEYVIEW(dev)) {
674 // } else if (IS_VALLEYVIEW(dev)) {
873 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
885 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
903 if (port == PORT_A && !IS_VALLEYVIEW(dev))
924 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
925 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
969 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1004 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1005 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1034 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1035 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1112 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1144 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1177 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1201 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1304 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1393 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
1403 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
1405 if (!IS_VALLEYVIEW(dev))
1431 if (IS_VALLEYVIEW(dev)) {
1447 if (dport->port == PORT_A && !IS_VALLEYVIEW(dev))
1450 if (IS_VALLEYVIEW(dev)) {
1480 if (!IS_VALLEYVIEW(dev))
1560 if (IS_VALLEYVIEW(dev))
1588 } else if (IS_VALLEYVIEW(dev)) {
1895 } else if (IS_VALLEYVIEW(dev)) {
2977 if (IS_VALLEYVIEW(dev)) {
3103 if (IS_VALLEYVIEW(dev))
3249 if (IS_VALLEYVIEW(dev))