Lines Matching refs:DRM_DEBUG_KMS
255 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
414 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
567 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
578 DRM_DEBUG_KMS("aux_ch native nack\n");
596 DRM_DEBUG_KMS("aux_i2c nack\n");
599 DRM_DEBUG_KMS("aux_i2c defer\n");
617 DRM_DEBUG_KMS("i2c_init %s\n", name);
716 DRM_DEBUG_KMS("DP link computation with max lane count %i "
765 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
768 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
803 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
811 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
927 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
941 DRM_DEBUG_KMS("Wait for panel power on\n");
947 DRM_DEBUG_KMS("Wait for panel power off time\n");
953 DRM_DEBUG_KMS("Wait for panel power cycle\n");
986 DRM_DEBUG_KMS("Turn eDP VDD on\n");
994 DRM_DEBUG_KMS("eDP VDD already on\n");
1009 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1015 DRM_DEBUG_KMS("eDP was not running\n");
1041 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1062 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1091 DRM_DEBUG_KMS("Turn eDP power on\n");
1094 DRM_DEBUG_KMS("eDP power already on\n");
1136 DRM_DEBUG_KMS("Turn eDP power off\n");
1166 DRM_DEBUG_KMS("\n");
1197 DRM_DEBUG_KMS("\n");
1219 DRM_DEBUG_KMS("\n");
1335 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1811 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1842 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1876 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1909 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2088 DRM_DEBUG_KMS("clock recovery OK\n");
2100 DRM_DEBUG_KMS("too many full retries, give up\n");
2112 DRM_DEBUG_KMS("too many voltage retries, give up\n");
2189 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2231 DRM_DEBUG_KMS("\n");
2290 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2321 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2325 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2401 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2445 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2699 DRM_DEBUG_KMS("no scaling not supported\n");
2893 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2910 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2933 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2937 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2992 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
3122 DRM_DEBUG_KMS("Adding %s connector on port %c\n",