Lines Matching defs:pipe_config
638 struct intel_crtc_config *pipe_config, int link_bw)
644 pipe_config->dpll.p1 = 2;
645 pipe_config->dpll.p2 = 10;
646 pipe_config->dpll.n = 2;
647 pipe_config->dpll.m1 = 23;
648 pipe_config->dpll.m2 = 8;
650 pipe_config->dpll.p1 = 1;
651 pipe_config->dpll.p2 = 10;
652 pipe_config->dpll.n = 1;
653 pipe_config->dpll.m1 = 14;
654 pipe_config->dpll.m2 = 2;
656 pipe_config->clock_set = true;
661 pipe_config->dpll.n = 1;
662 pipe_config->dpll.p1 = 2;
663 pipe_config->dpll.p2 = 10;
664 pipe_config->dpll.m1 = 12;
665 pipe_config->dpll.m2 = 9;
667 pipe_config->dpll.n = 2;
668 pipe_config->dpll.p1 = 1;
669 pipe_config->dpll.p2 = 10;
670 pipe_config->dpll.m1 = 14;
671 pipe_config->dpll.m2 = 8;
673 pipe_config->clock_set = true;
681 struct intel_crtc_config *pipe_config)
685 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
698 pipe_config->has_pch_encoder = true;
700 pipe_config->has_dp_encoder = true;
706 intel_gmch_panel_fitting(intel_crtc, pipe_config,
709 intel_pch_panel_fitting(intel_crtc, pipe_config,
722 bpp = pipe_config->pipe_bpp;
758 pipe_config->limited_color_range = true;
762 pipe_config->pipe_bpp = bpp;
763 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
767 pipe_config->port_clock, bpp);
772 adjusted_mode->clock, pipe_config->port_clock,
773 &pipe_config->dp_m_n);
775 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
1343 struct intel_crtc_config *pipe_config)
1376 pipe_config->adjusted_mode.flags |= flags;