Lines Matching defs:lane
100 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
716 DRM_DEBUG_KMS("DP link computation with max lane count %i "
765 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1483 /* Program Tx lane resets to default */
1725 int lane;
1729 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1730 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1731 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
1747 for (lane = 0; lane < 4; lane++)
1748 intel_dp->train_set[lane] = v | p;