Lines Matching defs:intel_dp
49 * @intel_dp: DP struct
54 static bool is_edp(struct intel_dp *intel_dp)
56 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
61 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
63 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
68 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
73 static void intel_dp_link_down(struct intel_dp *intel_dp);
76 intel_dp_max_link_bw(struct intel_dp *intel_dp)
78 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
129 struct intel_dp *intel_dp = intel_attached_dp(connector);
135 if (is_edp(intel_dp) && fixed_mode) {
145 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
146 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
220 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
222 struct drm_device *dev = intel_dp_to_dev(intel_dp);
230 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
232 struct drm_device *dev = intel_dp_to_dev(intel_dp);
241 intel_dp_check_edp(struct intel_dp *intel_dp)
243 struct drm_device *dev = intel_dp_to_dev(intel_dp);
247 if (!is_edp(intel_dp))
253 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
262 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
264 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
267 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
286 intel_dp_aux_ch(struct intel_dp *intel_dp,
290 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
293 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
306 intel_dp_check_edp(intel_dp);
373 // status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
436 intel_dp_aux_native_write(struct intel_dp *intel_dp,
444 intel_dp_check_edp(intel_dp);
454 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
469 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
472 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
477 intel_dp_aux_native_read(struct intel_dp *intel_dp,
487 intel_dp_check_edp(intel_dp);
497 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
520 struct intel_dp *intel_dp = container_of(adapter,
521 struct intel_dp,
531 intel_dp_check_edp(intel_dp);
563 ret = intel_dp_aux_ch(intel_dp,
613 intel_dp_i2c_init(struct intel_dp *intel_dp,
618 intel_dp->algo.running = false;
619 intel_dp->algo.address = 0;
620 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
622 memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));
625 strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
626 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
627 intel_dp->adapter.algo_data = &intel_dp->algo;
630 ironlake_edp_panel_vdd_on(intel_dp);
631 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
632 ironlake_edp_panel_vdd_off(intel_dp, false);
686 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
687 enum port port = dp_to_dig_port(intel_dp)->port;
689 struct intel_connector *intel_connector = intel_dp->attached_connector;
691 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
692 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
702 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
723 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp)
745 if (intel_dp->color_range_auto) {
752 intel_dp->color_range = DP_COLOR_RANGE_16_235;
754 intel_dp->color_range = 0;
757 if (intel_dp->color_range)
760 intel_dp->link_bw = bws[clock];
761 intel_dp->lane_count = (uint8_t)lane_count;
763 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
766 intel_dp->link_bw, intel_dp->lane_count,
775 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
780 void intel_dp_init_link_config(struct intel_dp *intel_dp)
782 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
783 intel_dp->link_configuration[0] = intel_dp->link_bw;
784 intel_dp->link_configuration[1] = intel_dp->lane_count;
785 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
789 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
790 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
791 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
795 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
797 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
813 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
816 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
832 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
833 enum port port = dp_to_dig_port(intel_dp)->port;
856 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
859 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
860 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
862 if (intel_dp->has_audio) {
865 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
869 intel_dp_init_link_config(intel_dp);
875 intel_dp->DP |= DP_SYNC_HS_HIGH;
877 intel_dp->DP |= DP_SYNC_VS_HIGH;
878 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
880 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
881 intel_dp->DP |= DP_ENHANCED_FRAMING;
883 intel_dp->DP |= crtc->pipe << 29;
886 intel_dp->DP |= intel_dp->color_range;
889 intel_dp->DP |= DP_SYNC_HS_HIGH;
891 intel_dp->DP |= DP_SYNC_VS_HIGH;
892 intel_dp->DP |= DP_LINK_TRAIN_OFF;
894 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
895 intel_dp->DP |= DP_ENHANCED_FRAMING;
898 intel_dp->DP |= DP_PIPEB_SELECT;
900 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
904 ironlake_set_pll_cpu_edp(intel_dp);
916 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
920 struct drm_device *dev = intel_dp_to_dev(intel_dp);
939 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
942 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
945 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
948 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
951 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
954 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
962 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
964 struct drm_device *dev = intel_dp_to_dev(intel_dp);
977 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
979 struct drm_device *dev = intel_dp_to_dev(intel_dp);
984 if (!is_edp(intel_dp))
988 if(intel_dp->want_panel_vdd)
991 intel_dp->want_panel_vdd = true;
993 if (ironlake_edp_have_panel_vdd(intel_dp)) {
998 if (!ironlake_edp_have_panel_power(intel_dp))
999 ironlake_wait_panel_power_cycle(intel_dp);
1001 pp = ironlake_get_pp_control(intel_dp);
1014 if (!ironlake_edp_have_panel_power(intel_dp)) {
1016 msleep(intel_dp->panel_power_up_delay);
1020 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1022 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1030 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1031 pp = ironlake_get_pp_control(intel_dp);
1043 msleep(intel_dp->panel_power_down_delay);
1049 struct intel_dp *intel_dp = (struct intel_dp *)dp;
1050 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1053 ironlake_panel_vdd_off_sync(intel_dp);
1057 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1059 if (!is_edp(intel_dp))
1062 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1063 if(!intel_dp->want_panel_vdd)
1066 intel_dp->want_panel_vdd = false;
1069 ironlake_panel_vdd_off_sync(intel_dp);
1076 intel_dp->vdd_worktimer_id = timeout(ironlake_panel_vdd_work, (void *)intel_dp,
1077 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1081 void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1083 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1088 if (!is_edp(intel_dp))
1093 if (ironlake_edp_have_panel_power(intel_dp)) {
1098 ironlake_wait_panel_power_cycle(intel_dp);
1100 pp = ironlake_get_pp_control(intel_dp);
1117 ironlake_wait_panel_on(intel_dp);
1126 void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1128 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1133 if (!is_edp(intel_dp))
1138 if(!intel_dp->want_panel_vdd)
1141 pp = ironlake_get_pp_control(intel_dp);
1149 intel_dp->want_panel_vdd = false;
1151 ironlake_wait_panel_off(intel_dp);
1154 void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1156 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1163 if (!is_edp(intel_dp))
1173 msleep(intel_dp->backlight_on_delay);
1174 pp = ironlake_get_pp_control(intel_dp);
1185 void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1187 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1192 if (!is_edp(intel_dp))
1198 pp = ironlake_get_pp_control(intel_dp);
1205 msleep(intel_dp->backlight_off_delay);
1208 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1210 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1226 /* We don't adjust intel_dp->DP while tearing down the link, to
1229 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1230 intel_dp->DP |= DP_PLL_ENABLE;
1231 I915_WRITE(DP_A, intel_dp->DP);
1236 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1238 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1254 * intel_dp->DP because link_down must not change that (otherwise link
1263 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1268 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1272 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1282 ret = intel_dp_aux_native_write_1(intel_dp,
1295 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1296 enum port port = dp_to_dig_port(intel_dp)->port;
1299 u32 tmp = I915_READ(intel_dp->output_reg);
1313 switch (intel_dp->output_reg) {
1336 intel_dp->output_reg);
1345 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1349 enum port port = dp_to_dig_port(intel_dp)->port;
1353 tmp = I915_READ(intel_dp->output_reg);
1381 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1382 enum port port = dp_to_dig_port(intel_dp)->port;
1387 ironlake_edp_panel_vdd_on(intel_dp);
1388 ironlake_edp_backlight_off(intel_dp);
1389 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1390 ironlake_edp_panel_off(intel_dp);
1394 intel_dp_link_down(intel_dp);
1399 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1400 enum port port = dp_to_dig_port(intel_dp)->port;
1404 intel_dp_link_down(intel_dp);
1406 ironlake_edp_pll_off(intel_dp);
1412 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1415 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1422 ironlake_edp_panel_vdd_on(intel_dp);
1423 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1424 intel_dp_start_link_train(intel_dp);
1425 ironlake_edp_panel_on(intel_dp);
1426 ironlake_edp_panel_vdd_off(intel_dp, true);
1427 intel_dp_complete_link_train(intel_dp);
1428 intel_dp_stop_link_train(intel_dp);
1429 ironlake_edp_backlight_on(intel_dp);
1442 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1443 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1448 ironlake_edp_pll_on(intel_dp);
1504 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1514 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1529 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1531 return intel_dp_aux_native_read_retry(intel_dp,
1555 intel_dp_voltage_max(struct intel_dp *intel_dp)
1557 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1558 enum port port = dp_to_dig_port(intel_dp)->port;
1571 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1573 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1574 enum port port = dp_to_dig_port(intel_dp)->port;
1625 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
1627 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1629 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1632 uint8_t train_set = intel_dp->train_set[0];
1721 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1729 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1739 voltage_max = intel_dp_voltage_max(intel_dp);
1743 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1748 intel_dp->train_set[lane] = v | p;
1884 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
1886 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1890 uint8_t train_set = intel_dp->train_set[0];
1896 signal_levels = intel_vlv_signal_levels(intel_dp);
1915 intel_dp_set_link_train(struct intel_dp *intel_dp,
1919 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1990 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1991 POSTING_READ(intel_dp->output_reg);
1993 intel_dp_aux_native_write_1(intel_dp,
1999 ret = intel_dp_aux_native_write(intel_dp,
2001 intel_dp->train_set,
2002 intel_dp->lane_count);
2003 if (ret != intel_dp->lane_count)
2010 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2012 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2043 intel_dp_start_link_train(struct intel_dp *intel_dp)
2045 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2052 uint32_t DP = intel_dp->DP;
2058 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
2059 intel_dp->link_configuration,
2064 memset(intel_dp->train_set, 0, 4);
2070 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
2073 intel_dp_set_signal_levels(intel_dp, &DP);
2076 if (!intel_dp_set_link_train(intel_dp, DP,
2081 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2082 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2087 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2094 for (i = 0; i < intel_dp->lane_count; i++)
2095 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2097 if (i == intel_dp->lane_count) {
2103 memset(intel_dp->train_set, 0, 4);
2109 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2117 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2120 intel_get_adjust_train(intel_dp, link_status);
2123 intel_dp->DP = DP;
2127 intel_dp_complete_link_train(struct intel_dp *intel_dp)
2131 uint32_t DP = intel_dp->DP;
2142 intel_dp_link_down(intel_dp);
2146 intel_dp_set_signal_levels(intel_dp, &DP);
2149 if (!intel_dp_set_link_train(intel_dp, DP,
2154 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2155 if (!intel_dp_get_link_status(intel_dp, link_status))
2159 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2160 intel_dp_start_link_train(intel_dp);
2165 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2172 intel_dp_link_down(intel_dp);
2173 intel_dp_start_link_train(intel_dp);
2180 intel_get_adjust_train(intel_dp, link_status);
2184 intel_dp_set_idle_link_train(intel_dp);
2186 intel_dp->DP = DP;
2193 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2195 intel_dp_set_link_train(intel_dp, intel_dp->DP,
2200 intel_dp_link_down(struct intel_dp *intel_dp)
2202 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2208 uint32_t DP = intel_dp->DP;
2228 if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
2235 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2238 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2240 POSTING_READ(intel_dp->output_reg);
2246 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2258 I915_WRITE(intel_dp->output_reg, DP);
2267 POSTING_READ(intel_dp->output_reg);
2274 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2275 POSTING_READ(intel_dp->output_reg);
2276 msleep(intel_dp->panel_power_down_delay);
2280 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2282 // char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2284 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2285 sizeof(intel_dp->dpcd)) == 0)
2288 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2292 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2295 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2299 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2302 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2303 intel_dp->downstream_ports,
2311 intel_dp_probe_oui(struct intel_dp *intel_dp)
2315 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2318 ironlake_edp_panel_vdd_on(intel_dp);
2320 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2324 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2328 ironlake_edp_panel_vdd_off(intel_dp, false);
2332 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2336 ret = intel_dp_aux_native_read_retry(intel_dp,
2346 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2349 (void) intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2362 intel_dp_check_link_status(struct intel_dp *intel_dp)
2364 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2375 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2376 intel_dp_link_down(intel_dp);
2381 if (!intel_dp_get_dpcd(intel_dp)) {
2382 intel_dp_link_down(intel_dp);
2387 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2388 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2390 (void) intel_dp_aux_native_write_1(intel_dp,
2395 intel_dp_handle_test_request(intel_dp);
2400 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2403 intel_dp_start_link_train(intel_dp);
2404 intel_dp_complete_link_train(intel_dp);
2405 intel_dp_stop_link_train(intel_dp);
2411 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2413 uint8_t *dpcd = intel_dp->dpcd;
2417 if (!intel_dp_get_dpcd(intel_dp))
2425 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2428 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2436 if (drm_probe_ddc(&intel_dp->adapter))
2440 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2450 ironlake_dp_detect(struct intel_dp *intel_dp)
2452 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2454 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2458 if (is_edp(intel_dp)) {
2468 return intel_dp_detect_dpcd(intel_dp);
2472 g4x_dp_detect(struct intel_dp *intel_dp)
2474 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2476 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2480 if (is_edp(intel_dp)) {
2506 return intel_dp_detect_dpcd(intel_dp);
2556 struct intel_dp *intel_dp = intel_attached_dp(connector);
2557 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2563 intel_dp->has_audio = false;
2566 status = ironlake_dp_detect(intel_dp);
2568 status = g4x_dp_detect(intel_dp);
2573 intel_dp_probe_oui(intel_dp);
2575 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2576 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2578 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2580 intel_dp->has_audio = drm_detect_monitor_audio(edid);
2592 struct intel_dp *intel_dp = intel_attached_dp(connector);
2600 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2605 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2620 struct intel_dp *intel_dp = intel_attached_dp(connector);
2624 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2641 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2652 if (i == intel_dp->force_audio)
2655 intel_dp->force_audio = i;
2662 if (has_audio == intel_dp->has_audio)
2665 intel_dp->has_audio = has_audio;
2670 bool old_auto = intel_dp->color_range_auto;
2671 uint32_t old_range = intel_dp->color_range;
2675 intel_dp->color_range_auto = true;
2678 intel_dp->color_range_auto = false;
2679 intel_dp->color_range = 0;
2682 intel_dp->color_range_auto = false;
2683 intel_dp->color_range = DP_COLOR_RANGE_16_235;
2689 if (old_auto == intel_dp->color_range_auto &&
2690 old_range == intel_dp->color_range)
2696 if (is_edp(intel_dp) &&
2741 struct intel_dp *intel_dp = &intel_dig_port->dp;
2742 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2744 // i2c_del_adapter(&intel_dp->adapter);
2746 if (is_edp(intel_dp)) {
2747 if (intel_dp->vdd_worktimer_id != NULL) {
2748 (void) untimeout(intel_dp->vdd_worktimer_id);
2749 intel_dp->vdd_worktimer_id = NULL;
2752 ironlake_panel_vdd_off_sync(intel_dp);
2783 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2785 intel_dp_check_link_status(intel_dp);
2794 struct intel_dp *intel_dp;
2797 intel_dp = enc_to_intel_dp(&intel_encoder->base);
2801 return intel_dp->output_reg;
2828 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2834 intel_dp->color_range_auto = true;
2836 if (is_edp(intel_dp)) {
2848 struct intel_dp *intel_dp,
2870 pp = ironlake_get_pp_control(intel_dp);
2926 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2927 intel_dp->backlight_on_delay = get_delay(t8);
2928 intel_dp->backlight_off_delay = get_delay(t9);
2929 intel_dp->panel_power_down_delay = get_delay(t10);
2930 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2934 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2935 intel_dp->panel_power_cycle_delay);
2938 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2946 struct intel_dp *intel_dp,
2980 if (dp_to_dig_port(intel_dp)->port == PORT_A)
2998 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
3002 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3011 if (!is_edp(intel_dp))
3014 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3017 ironlake_edp_panel_vdd_on(intel_dp);
3018 has_dpcd = intel_dp_get_dpcd(intel_dp);
3019 ironlake_edp_panel_vdd_off(intel_dp, false);
3022 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3024 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3033 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3036 ironlake_edp_panel_vdd_on(intel_dp);
3037 edid = drm_get_edid(connector, &intel_dp->adapter);
3068 ironlake_edp_panel_vdd_off(intel_dp, false);
3081 struct intel_dp *intel_dp = &intel_dig_port->dp;
3090 intel_dp->DP = I915_READ(intel_dp->output_reg);
3091 intel_dp->attached_connector = intel_connector;
3132 intel_dp->vdd_worktimer_id = NULL;
3141 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3145 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3148 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3151 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3154 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3183 error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3188 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
3189 //i2c_del_adapter(&intel_dp->adapter);
3190 if (is_edp(intel_dp)) {
3191 if (intel_dp->vdd_worktimer_id != NULL) {
3192 (void) untimeout(intel_dp->vdd_worktimer_id);
3193 intel_dp->vdd_worktimer_id = NULL;
3196 ironlake_panel_vdd_off_sync(intel_dp);
3203 intel_dp_add_properties(intel_dp, connector);