Lines Matching refs:tmp
4749 uint32_t tmp;
4751 tmp = I915_READ(HTOTAL(cpu_transcoder));
4752 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4753 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4754 tmp = I915_READ(HBLANK(cpu_transcoder));
4755 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4756 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4757 tmp = I915_READ(HSYNC(cpu_transcoder));
4758 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4759 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4761 tmp = I915_READ(VTOTAL(cpu_transcoder));
4762 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4763 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4764 tmp = I915_READ(VBLANK(cpu_transcoder));
4765 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4766 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4767 tmp = I915_READ(VSYNC(cpu_transcoder));
4768 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4769 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4777 tmp = I915_READ(PIPESRC(crtc->pipe));
4778 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4779 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4965 uint32_t tmp;
4967 tmp = I915_READ(PFIT_CONTROL);
4968 if (!(tmp & PFIT_ENABLE))
4976 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4980 pipe_config->gmch_pfit.control = tmp;
4992 uint32_t tmp;
4997 tmp = I915_READ(PIPECONF(crtc->pipe));
4998 if (!(tmp & PIPECONF_ENABLE))
5006 tmp = I915_READ(DPLL_MD(crtc->pipe));
5008 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5011 tmp = I915_READ(DPLL(crtc->pipe));
5013 ((tmp & SDVO_MULTIPLIER_MASK)
5182 u32 tmp;
5201 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5202 tmp &= ~SBI_SSCCTL_DISABLE;
5203 tmp |= SBI_SSCCTL_PATHALT;
5204 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5208 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5209 tmp &= ~SBI_SSCCTL_PATHALT;
5210 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5213 tmp = I915_READ(SOUTH_CHICKEN2);
5214 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5215 I915_WRITE(SOUTH_CHICKEN2, tmp);
5221 tmp = I915_READ(SOUTH_CHICKEN2);
5222 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5223 I915_WRITE(SOUTH_CHICKEN2, tmp);
5231 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5232 tmp &= ~(0xFFUL << 24);
5233 tmp |= (0x12 << 24);
5234 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5237 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5238 tmp |= 0x7FFF;
5239 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5242 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5243 tmp |= (1 << 11);
5244 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5246 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5247 tmp |= (1 << 11);
5248 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5251 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5252 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5253 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5255 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5256 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5257 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5259 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5260 tmp |= (0x3F << 8);
5261 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5263 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5264 tmp |= (0x3F << 8);
5265 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5268 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5269 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5270 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5272 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5273 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5274 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5277 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5278 tmp &= ~(7 << 13);
5279 tmp |= (5 << 13);
5280 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5282 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5283 tmp &= ~(7 << 13);
5284 tmp |= (5 << 13);
5285 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5288 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5289 tmp &= ~0xFF;
5290 tmp |= 0x1C;
5291 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5293 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5294 tmp &= ~0xFF;
5295 tmp |= 0x1C;
5296 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5298 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5299 tmp &= ~(0xFF << 16);
5300 tmp |= (0x1C << 16);
5301 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5303 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5304 tmp &= ~(0xFF << 16);
5305 tmp |= (0x1C << 16);
5306 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5309 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5310 tmp |= (1 << 27);
5311 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5313 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5314 tmp |= (1 << 27);
5315 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5317 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5318 tmp &= ~(0xFUL << 28);
5319 tmp |= (4 << 28);
5320 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5322 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5323 tmp &= ~(0xFUL << 28);
5324 tmp |= (4 << 28);
5325 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5329 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5330 tmp |= SBI_DBUFF0_ENABLE;
5331 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5856 uint32_t tmp;
5858 tmp = I915_READ(PF_CTL(crtc->pipe));
5860 if (tmp & PF_ENABLE) {
5868 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5870 DRM_DEBUG("PF_CTL(crtc->pipe) 0x%x", tmp);
5880 uint32_t tmp;
5885 tmp = I915_READ(PIPECONF(crtc->pipe));
5886 if (!(tmp & PIPECONF_ENABLE))
5895 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5896 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5908 tmp = I915_READ(PCH_DPLL_SEL);
5909 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5996 uint32_t tmp;
6001 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6002 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6004 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6027 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
6028 if (!(tmp & PIPECONF_ENABLE))
6036 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6037 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6041 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6042 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6182 int tmp;
6194 tmp = I915_READ(aud_cntrl_st2);
6195 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6196 I915_WRITE(aud_cntrl_st2, tmp);
6202 tmp = I915_READ(aud_cntrl_st2);
6203 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6204 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6205 I915_WRITE(aud_cntrl_st2, tmp);
6206 tmp = I915_READ(aud_cntrl_st2);
6207 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6210 tmp = I915_READ(aud_config);
6211 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6213 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6214 I915_WRITE(aud_config, tmp);
6884 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7640 struct drm_crtc *tmp;
7647 list_for_each_entry(tmp, struct drm_crtc, &dev->mode_config.crtc_list, head) {
7648 if (tmp == crtc)