Lines Matching refs:set
450 * Returns whether the given set of divisors are valid for a given refclk with
495 * We haven't figured out how to reliably set up different
556 * We haven't figured out how to reliably set up different
782 /* Wait for vblank interrupt bit to set */
1533 /* Workaround: set timing override bit. */
2740 /* still set train pattern 1 */
2965 /* set transcoder timing */
3137 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3888 DRM_ERROR("encoder->connectors_active not set\n");
4341 * and set it to a reasonable value instead.
4879 * Returns a set of divisors for the desired target clock with the given
5442 * to BSpec, but reality doesn't agree. Just set them up in
5526 * Returns a set of divisors for the desired target clock with the given
6087 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6705 /* VESA 640x480x72Hz mode to set on the pipe */
6896 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7956 * bit set at most. */
8033 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8240 DRM_ERROR("encoder's active_connectors set, but no crtc\n");
8432 * Hence simply check whether any bit is set in modeset_pipes in all the
8456 * to set it here already despite that we pass it down the callchain.
8482 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8599 is_crtc_connector_off(struct drm_mode_set *set)
8603 if (set->num_connectors == 0)
8606 if ((set->connectors == NULL))
8609 for (i = 0; i < set->num_connectors; i++)
8610 if (set->connectors[i]->encoder &&
8611 set->connectors[i]->encoder->crtc == set->crtc &&
8612 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
8619 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8625 if (is_crtc_connector_off(set)) {
8627 } else if (set->crtc->fb != set->fb) {
8628 /* If we have no fb then treat it as a full mode set */
8629 if (set->crtc->fb == NULL) {
8630 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8632 } else if (set->fb == NULL) {
8634 } else if (set->fb->pixel_format !=
8635 set->crtc->fb->pixel_format) {
8642 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8645 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8646 DRM_DEBUG_KMS("modes are different, full mode set\n");
8647 drm_mode_debug_printmodeline(&set->crtc->mode);
8648 drm_mode_debug_printmodeline(set->mode);
8655 struct drm_mode_set *set,
8666 WARN_ON(!set->fb && (set->num_connectors != 0));
8667 WARN_ON(set->fb && (set->num_connectors == 0));
8674 for (ro = 0; ro < set->num_connectors; ro++) {
8675 if (set->connectors[ro] == &connector->base) {
8684 if ((!set->fb || ro == set->num_connectors) &&
8686 connector->base.encoder->crtc == set->crtc) {
8711 for (ro = 0; ro < set->num_connectors; ro++) {
8712 if (set->connectors[ro] == &connector->base)
8713 new_crtc = set->crtc;
8755 static int intel_crtc_set_config(struct drm_mode_set *set)
8762 BUG_ON(!set);
8763 BUG_ON(!set->crtc);
8764 BUG_ON(!set->crtc->helper_private);
8767 BUG_ON(!set->mode && set->fb);
8768 BUG_ON(set->fb && set->num_connectors == 0);
8770 if (set->fb) {
8772 set->crtc->base.id, set->fb->base.id,
8773 (int)set->num_connectors, set->x, set->y);
8775 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8778 dev = set->crtc->dev;
8789 save_set.crtc = set->crtc;
8790 save_set.mode = &set->crtc->mode;
8791 save_set.x = set->crtc->x;
8792 save_set.y = set->crtc->y;
8793 save_set.fb = set->crtc->fb;
8799 intel_set_config_compute_mode_changes(set, config);
8801 ret = intel_modeset_stage_output_state(dev, set, config);
8806 if ((set->mode == NULL) && set->fb) {
8807 DRM_DEBUG_KMS("fb changed without set->mode");
8812 ret = intel_set_mode(set->crtc, set->mode,
8813 set->x, set->y, set->fb);
8815 intel_crtc_wait_for_pending_flips(set->crtc);
8817 ret = intel_pipe_set_base(set->crtc,
8818 set->x, set->y, set->fb);
8822 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
8823 set->crtc->base.id, ret);
9469 * BLM_PCH_PWM_ENABLE is set.
9685 /* We can't just switch on the pipe A, we need to set things up with a
10082 * set vga decode state - true == enable VGA decode