Lines Matching refs:pipe_bpp
4033 pipe_config->pipe_bpp);
4037 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4042 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4043 pipe_config->pipe_bpp -= 2*3;
4045 pipe_config->pipe_bpp);
4063 pipe_config->pipe_bpp == 24;
4092 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4093 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4094 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4097 pipe_config->pipe_bpp = 8*3;
4805 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4809 switch (intel_crtc->config.pipe_bpp) {
5382 switch (intel_crtc->config.pipe_bpp) {
7707 int bpp = pipe_config->pipe_bpp;
7718 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7725 pipe_config->pipe_bpp = 24;
7774 pipe_config->pipe_bpp = bpp;
7798 pipe_config->pipe_bpp, pipe_config->dither);
7864 /* Compute a starting value for pipe_config->pipe_bpp taking the source
7929 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7931 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);