Lines Matching refs:pipe
434 * Returns whether any output on the specified pipe is of the specified type
729 enum pipe pipe)
731 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
737 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
740 u32 frame, frame_reg = PIPEFRAME(pipe);
749 * intel_wait_for_vblank - wait for vblank on a given pipe
751 * @pipe: pipe to wait for
753 * Wait for vblank to occur on a given pipe. Needed for various bits of
756 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
759 int pipestat_reg = PIPESTAT(pipe);
762 ironlake_wait_for_vblank(dev, pipe);
790 * intel_wait_for_pipe_off - wait for pipe to turn off
792 * @pipe: pipe to wait for
794 * After disabling a pipe, we can't wait for vblank in the usual way,
796 * see an interrupt when the pipe is disabled.
799 * wait for the pipe register state bit to turn off
806 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
810 pipe);
821 int reg = PIPEDSL(pipe);
892 enum pipe pipe, bool state)
898 reg = DPLL(pipe);
946 enum pipe pipe, bool state)
952 pipe);
960 reg = FDI_TX_CTL(pipe);
972 enum pipe pipe, bool state)
978 reg = FDI_RX_CTL(pipe);
989 enum pipe pipe)
1002 reg = FDI_TX_CTL(pipe);
1009 enum pipe pipe)
1014 reg = FDI_RX_CTL(pipe);
1021 enum pipe pipe)
1025 enum pipe panel_pipe = PIPE_A;
1044 if(panel_pipe == pipe && locked)
1045 DRM_ERROR("panel assertion failure, pipe %c regs locked\n",
1046 pipe_name(pipe));
1050 enum pipe pipe, bool state)
1056 pipe);
1058 /* if we need the pipe A quirk it must be always on */
1059 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1072 DRM_ERROR("pipe %c assertion failure (expected %s, current %s)\n",
1073 pipe_name(pipe), state_string(state), state_string(cur_state));
1095 enum pipe pipe)
1104 reg = DSPCNTR(pipe);
1108 plane_name(pipe));
1112 /* Need to check both planes against the pipe */
1118 if((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe)
1119 DRM_ERROR("plane %c assertion failure, should be off on pipe %c but is still active\n",
1120 plane_name(i), pipe_name(pipe));
1125 enum pipe pipe)
1133 reg = SPCNTR(pipe, i);
1136 DRM_ERROR("sprite %c assertion failure, should be off on pipe %c but is still active\n",
1137 sprite_name(pipe, i), pipe_name(pipe));
1140 reg = SPRCTL(pipe);
1143 DRM_ERROR("sprite %c assertion failure, should be off on pipe %c but is still active\n",
1144 plane_name(pipe), pipe_name(pipe));
1146 reg = DVSCNTR(pipe);
1149 DRM_ERROR("sprite %c assertion failure, should be off on pipe %c but is still active\n",
1150 plane_name(pipe), pipe_name(pipe));
1172 enum pipe pipe)
1178 reg = PCH_TRANSCONF(pipe);
1182 DRM_ERROR("transcoder assertion failed, should be off on pipe %c but is still active\n",
1183 pipe_name(pipe));
1187 enum pipe pipe, u32 port_sel, u32 val)
1193 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1198 if ((val & DP_PIPE_MASK) != (pipe << 30))
1205 enum pipe pipe, u32 val)
1211 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1214 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1221 enum pipe pipe, u32 val)
1227 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1230 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1237 enum pipe pipe, u32 val)
1242 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1245 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1252 enum pipe pipe, int reg, u32 port_sel)
1255 if(dp_pipe_enabled(dev_priv, pipe, port_sel, val))
1257 reg, pipe_name(pipe));
1265 enum pipe pipe, int reg)
1268 if(hdmi_pipe_enabled(dev_priv, pipe, val))
1270 reg, pipe_name(pipe));
1278 enum pipe pipe)
1283 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1284 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1285 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1289 if(adpa_pipe_enabled(dev_priv, pipe, val))
1291 pipe_name(pipe));
1295 if(lvds_pipe_enabled(dev_priv, pipe, val))
1297 pipe_name(pipe));
1299 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1300 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1301 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1307 * @pipe: pipe PLL to enable
1309 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1317 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1322 assert_pipe_disabled(dev_priv, pipe);
1329 assert_panel_unlocked(dev_priv, pipe);
1331 reg = DPLL(pipe);
1350 * @pipe: pipe PLL to disable
1352 * Disable the PLL for @pipe, making sure the pipe is off first.
1356 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1361 /* Don't disable pipe A or pipe A PLLs if needed */
1362 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1365 /* Make sure the pipe isn't still relying on us */
1366 assert_pipe_disabled(dev_priv, pipe);
1368 reg = DPLL(pipe);
1392 * @pipe: pipe PLL to enable
1466 enum pipe pipe)
1469 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1481 assert_fdi_tx_enabled(dev_priv, pipe);
1482 assert_fdi_rx_enabled(dev_priv, pipe);
1487 reg = TRANS_CHICKEN2(pipe);
1493 reg = PCH_TRANSCONF(pipe);
1495 pipeconf_val = I915_READ(PIPECONF(pipe));
1518 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1530 assert_fdi_tx_enabled(dev_priv, (enum pipe)cpu_transcoder);
1531 assert_fdi_rx_enabled(dev_priv, (enum pipe)TRANSCODER_A);
1553 enum pipe pipe)
1559 assert_fdi_tx_disabled(dev_priv, pipe);
1560 assert_fdi_rx_disabled(dev_priv, pipe);
1563 assert_pch_ports_disabled(dev_priv, pipe);
1565 reg = PCH_TRANSCONF(pipe);
1571 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1575 reg = TRANS_CHICKEN2(pipe);
1600 * intel_enable_pipe - enable a pipe, asserting requirements
1602 * @pipe: pipe to enable
1603 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1605 * Enable @pipe, making sure that various hardware specific requirements
1608 * @pipe should be %PIPE_A or %PIPE_B.
1610 * Will wait until the pipe is actually running (i.e. first vblank) before
1613 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1617 pipe);
1618 enum pipe pch_transcoder;
1622 assert_planes_disabled(dev_priv, pipe);
1623 assert_sprites_disabled(dev_priv, pipe);
1626 pch_transcoder = (enum pipe)TRANSCODER_A;
1628 pch_transcoder = pipe;
1631 * A pipe without a PLL won't actually be able to drive bits from
1632 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1636 assert_pll_enabled(dev_priv, pipe);
1642 (enum pipe) cpu_transcoder);
1653 intel_wait_for_vblank(dev_priv->dev, pipe);
1657 * intel_disable_pipe - disable a pipe, asserting requirements
1659 * @pipe: pipe to disable
1661 * Disable @pipe, making sure that various hardware specific requirements
1664 * @pipe should be %PIPE_A or %PIPE_B.
1666 * Will wait until the pipe has shut down before returning.
1669 enum pipe pipe)
1672 pipe);
1680 assert_planes_disabled(dev_priv, pipe);
1681 assert_sprites_disabled(dev_priv, pipe);
1683 /* Don't disable pipe A or pipe A PLLs if needed */
1684 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1693 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1710 * intel_enable_plane - enable a display plane on a given pipe
1713 * @pipe: pipe being fed
1715 * Enable @plane on @pipe, making sure that @pipe is running first.
1718 enum plane plane, enum pipe pipe)
1723 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1724 assert_pipe_enabled(dev_priv, pipe);
1733 intel_wait_for_vblank(dev_priv->dev, pipe);
1740 * @pipe: pipe consuming the data
1745 enum plane plane, enum pipe pipe)
1757 intel_wait_for_vblank(dev_priv->dev, pipe);
2149 switch (intel_crtc->pipe) {
2211 intel_wait_for_vblank(dev, intel_crtc->pipe);
2228 int pipe = intel_crtc->pipe;
2232 reg = FDI_TX_CTL(pipe);
2243 reg = FDI_RX_CTL(pipe);
2301 int pipe = intel_crtc->pipe;
2305 /* FDI needs bits from pipe & plane first */
2306 assert_pipe_enabled(dev_priv, pipe);
2311 reg = FDI_RX_IMR(pipe);
2320 reg = FDI_TX_CTL(pipe);
2328 reg = FDI_RX_CTL(pipe);
2338 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2339 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2342 reg = FDI_RX_IIR(pipe);
2357 reg = FDI_TX_CTL(pipe);
2363 reg = FDI_RX_CTL(pipe);
2372 reg = FDI_RX_IIR(pipe);
2403 int pipe = intel_crtc->pipe;
2408 reg = FDI_RX_IMR(pipe);
2418 reg = FDI_TX_CTL(pipe);
2429 I915_WRITE(FDI_RX_MISC(pipe),
2432 reg = FDI_RX_CTL(pipe);
2447 reg = FDI_TX_CTL(pipe);
2457 reg = FDI_RX_IIR(pipe);
2474 reg = FDI_TX_CTL(pipe);
2485 reg = FDI_RX_CTL(pipe);
2500 reg = FDI_TX_CTL(pipe);
2510 reg = FDI_RX_IIR(pipe);
2535 int pipe = intel_crtc->pipe;
2540 reg = FDI_RX_IMR(pipe);
2550 I915_READ(FDI_RX_IIR(pipe)));
2553 reg = FDI_TX_CTL(pipe);
2564 I915_WRITE(FDI_RX_MISC(pipe),
2567 reg = FDI_RX_CTL(pipe);
2579 reg = FDI_TX_CTL(pipe);
2588 reg = FDI_RX_IIR(pipe);
2603 reg = FDI_TX_CTL(pipe);
2611 reg = FDI_RX_CTL(pipe);
2621 reg = FDI_TX_CTL(pipe);
2630 reg = FDI_RX_IIR(pipe);
2650 int pipe = intel_crtc->pipe;
2655 reg = FDI_RX_CTL(pipe);
2659 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2673 reg = FDI_TX_CTL(pipe);
2687 int pipe = intel_crtc->pipe;
2691 reg = FDI_RX_CTL(pipe);
2696 reg = FDI_TX_CTL(pipe);
2703 reg = FDI_RX_CTL(pipe);
2717 int pipe = intel_crtc->pipe;
2721 reg = FDI_TX_CTL(pipe);
2726 reg = FDI_RX_CTL(pipe);
2729 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2737 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2741 reg = FDI_TX_CTL(pipe);
2747 reg = FDI_RX_CTL(pipe);
2758 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2894 enum pipe pch_transcoder)
2930 int pipe = intel_crtc->pipe;
2933 assert_pch_transcoder_disabled(dev_priv, pipe);
2937 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2938 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2956 temp |= TRANS_DPLL_ENABLE(pipe);
2957 sel = TRANS_DPLLB_SEL(pipe);
2966 assert_panel_unlocked(dev_priv, pipe);
2967 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
2975 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
2976 reg = TRANS_DP_CTL(pipe);
3007 ironlake_enable_pch_transcoder(dev_priv, pipe);
3017 assert_pch_transcoder_disabled(dev_priv, (enum pipe) TRANSCODER_A);
3062 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3063 i = (enum intel_dpll_id)crtc->pipe;
3103 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3104 pipe_name(crtc->pipe));
3127 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3130 int dslreg = PIPEDSL(pipe);
3137 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3145 int pipe = crtc->pipe;
3153 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3154 PF_PIPE_SEL_IVB(pipe));
3156 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3157 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3158 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3165 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3169 if (intel_plane->pipe == pipe)
3176 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3180 if (intel_plane->pipe == pipe)
3190 int pipe = intel_crtc->pipe;
3201 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3202 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3219 assert_fdi_tx_disabled(dev_priv, pipe);
3220 assert_fdi_rx_disabled(dev_priv, pipe);
3230 * On ILK+ LUT must be loaded before the pipe is running but with
3235 intel_enable_pipe(dev_priv, pipe,
3237 intel_enable_plane(dev_priv, plane, pipe);
3252 cpt_verify_modeset(dev, intel_crtc->pipe);
3256 * outputs) where an enabled pipe still completes any pageflip right
3257 * away (as if the pipe is off) instead of waiting for vblank. As soon
3262 intel_wait_for_vblank(dev, intel_crtc->pipe);
3265 /* IPS only exists on ULT machines and is tied to pipe A. */
3268 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3298 intel_wait_for_vblank(dev, crtc->pipe);
3307 int pipe = intel_crtc->pipe;
3317 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3335 * On ILK+ LUT must be loaded before the pipe is running but with
3343 intel_enable_pipe(dev_priv, pipe,
3345 intel_enable_plane(dev_priv, plane, pipe);
3363 * outputs) where an enabled pipe still completes any pageflip right
3364 * away (as if the pipe is off) instead of waiting for vblank. As soon
3369 intel_wait_for_vblank(dev, intel_crtc->pipe);
3376 int pipe = crtc->pipe;
3381 I915_WRITE(PF_CTL(pipe), 0);
3382 I915_WRITE(PF_WIN_POS(pipe), 0);
3383 I915_WRITE(PF_WIN_SZ(pipe), 0);
3393 int pipe = intel_crtc->pipe;
3405 drm_vblank_off(dev, pipe);
3412 intel_disable_plane(dev_priv, plane, pipe);
3415 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3417 intel_disable_pipe(dev_priv, pipe);
3428 ironlake_disable_pch_transcoder(dev_priv, pipe);
3429 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3433 reg = TRANS_DP_CTL(pipe);
3442 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3466 int pipe = intel_crtc->pipe;
3477 drm_vblank_off(dev, pipe);
3487 intel_disable_plane(dev_priv, plane, pipe);
3491 intel_disable_pipe(dev_priv, pipe);
3554 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3556 u32 cntl = I915_READ(CURCNTR(pipe));
3562 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3563 intel_wait_for_vblank(dev_priv->dev, pipe);
3564 I915_WRITE(CURCNTR(pipe), cntl);
3565 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3580 * The panel fitter should only be adjusted whilst the pipe is disabled,
3584 assert_pipe_disabled(dev_priv, crtc->pipe);
3591 I915_WRITE(BCLRPAT(crtc->pipe), 0);
3600 int pipe = intel_crtc->pipe;
3617 intel_enable_pll(dev_priv, pipe);
3623 /* VLV wants encoder enabling _before_ the pipe is up. */
3631 intel_enable_pipe(dev_priv, pipe, false);
3632 intel_enable_plane(dev_priv, plane, pipe);
3647 int pipe = intel_crtc->pipe;
3658 intel_enable_pll(dev_priv, pipe);
3668 intel_enable_pipe(dev_priv, pipe, false);
3669 intel_enable_plane(dev_priv, plane, pipe);
3673 g4x_fixup_plane(dev_priv, pipe);
3676 /* Give the overlay scaler a chance to enable if it's on this pipe */
3693 assert_pipe_disabled(dev_priv, crtc->pipe);
3706 int pipe = intel_crtc->pipe;
3715 /* Give the overlay scaler a chance to disable if it's on this pipe */
3717 drm_vblank_off(dev, pipe);
3725 intel_disable_plane(dev_priv, plane, pipe);
3727 intel_disable_pipe(dev_priv, pipe);
3735 intel_disable_pll(dev_priv, pipe);
3752 int pipe = intel_crtc->pipe;
3761 switch (pipe) {
3771 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3777 * Sets the power management mode of the pipe and plane.
3813 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3855 * state of the entire output pipe. */
3877 enum pipe pipe;
3890 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3904 if (pipe != to_intel_crtc(crtc)->pipe)
3905 DRM_ERROR("encoder active on the wrong pipe\n");
3939 enum pipe pipe = 0;
3942 return encoder->get_hw_state(encoder, &pipe);
3945 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3952 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3953 pipe_name(pipe), pipe_config->fdi_lanes);
3955 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3956 pipe_name(pipe), pipe_config->fdi_lanes);
3973 /* Ivybridge 3 pipe is really complicated */
3974 switch (pipe) {
3980 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3981 pipe_name(pipe), pipe_config->fdi_lanes);
3989 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3990 pipe_name(pipe), pipe_config->fdi_lanes);
4041 intel_crtc->pipe, pipe_config);
4044 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4095 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4310 int pipe = crtc->pipe;
4323 I915_WRITE(FP0(pipe), fp);
4328 I915_WRITE(FP1(pipe), fp2);
4331 I915_WRITE(FP1(pipe), fp);
4368 int pipe = crtc->pipe;
4370 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4371 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4372 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4373 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4381 int pipe = crtc->pipe;
4390 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4391 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4392 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4393 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4410 int pipe = crtc->pipe;
4426 if (pipe)
4433 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4435 vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4452 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4455 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4461 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4464 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4470 if (!pipe)
4471 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4474 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4478 if (!pipe)
4479 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4482 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4486 coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4491 vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4493 vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4502 if (pipe)
4506 I915_WRITE(DPLL(pipe), dpll);
4507 POSTING_READ(DPLL(pipe));
4510 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4511 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4515 I915_WRITE(DPLL_MD(pipe), dpll_md);
4516 POSTING_READ(DPLL_MD(pipe));
4531 int pipe = crtc->pipe;
4593 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4594 POSTING_READ(DPLL(pipe));
4604 I915_WRITE(DPLL(pipe), dpll);
4607 POSTING_READ(DPLL(pipe));
4613 I915_WRITE(DPLL_MD(pipe), dpll_md);
4620 I915_WRITE(DPLL(pipe), dpll);
4631 int pipe = crtc->pipe;
4657 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4658 POSTING_READ(DPLL(pipe));
4665 I915_WRITE(DPLL(pipe), dpll);
4668 POSTING_READ(DPLL(pipe));
4676 I915_WRITE(DPLL(pipe), dpll);
4683 enum pipe pipe = intel_crtc->pipe;
4733 (pipe == PIPE_B || pipe == PIPE_C))
4734 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4739 I915_WRITE(PIPESRC(pipe),
4777 tmp = I915_READ(PIPESRC(crtc->pipe));
4790 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4794 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4795 * pipe == 0 check?
4843 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4844 POSTING_READ(PIPECONF(intel_crtc->pipe));
4855 int pipe = intel_crtc->pipe;
4932 if (pipe == 0)
4971 /* Check whether the pfit is attached to our pipe. */
4973 if (crtc->pipe != PIPE_B)
4976 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4994 pipe_config->cpu_transcoder = (enum transcoder)crtc->pipe;
4997 tmp = I915_READ(PIPECONF(crtc->pipe));
5006 tmp = I915_READ(DPLL_MD(crtc->pipe));
5011 tmp = I915_READ(DPLL(crtc->pipe));
5377 int pipe = intel_crtc->pipe;
5411 I915_WRITE(PIPECONF(pipe), val);
5412 POSTING_READ(PIPECONF(pipe));
5416 * Set up the pipe CSC unit.
5427 int pipe = intel_crtc->pipe;
5431 * TODO: Check what kind of values actually come out of the pipe
5445 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5446 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5448 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5449 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5451 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5452 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5454 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5455 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5456 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5464 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5465 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5466 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5468 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5475 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5499 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5500 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5577 switch (intel_crtc->pipe) {
5705 int pipe = intel_crtc->pipe;
5766 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5767 pipe_name(pipe));
5858 tmp = I915_READ(PF_CTL(crtc->pipe));
5861 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5862 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5869 PF_PIPE_SEL_IVB(crtc->pipe));
5870 DRM_DEBUG("PF_CTL(crtc->pipe) 0x%x", tmp);
5882 pipe_config->cpu_transcoder = (enum transcoder)crtc->pipe;
5885 tmp = I915_READ(PIPECONF(crtc->pipe));
5889 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5895 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5906 pipe_config->shared_dpll = (enum intel_dpll_id)crtc->pipe;
5909 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5939 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5998 pipe_config->cpu_transcoder = (enum transcoder)crtc->pipe;
6003 enum pipe trans_edp_pipe;
6006 DRM_ERROR("unknown pipe linked to edp transcoder\n");
6019 if (trans_edp_pipe == crtc->pipe)
6033 * DDI E. So just check whether this pipe is wired to DDI E and whether
6050 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6074 int pipe = intel_crtc->pipe;
6077 drm_vblank_pre_modeset(dev, pipe);
6081 drm_vblank_post_modeset(dev, pipe);
6181 int pipe = to_intel_crtc(crtc)->pipe;
6184 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6185 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6186 int aud_config = HSW_AUD_CFG(pipe);
6195 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6199 intel_wait_for_vblank(dev, pipe);
6204 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6216 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6218 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6270 int pipe = to_intel_crtc(crtc)->pipe;
6273 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6274 aud_config = IBX_AUD_CFG(pipe);
6275 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6278 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6279 aud_config = CPT_AUD_CFG(pipe);
6280 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6284 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6363 enum pipe pipe = intel_crtc->pipe;
6364 int palreg = PALETTE(pipe);
6373 assert_pll_enabled(dev_priv, pipe);
6377 palreg = LGC_PALETTE(pipe);
6379 /* Workaround : Do not read or write the pipe palette/gamma data while
6383 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6435 int pipe = intel_crtc->pipe;
6439 uint32_t cntl = I915_READ(CURCNTR(pipe));
6443 cntl |= pipe << 28; /* Connect to correct pipe */
6448 I915_WRITE(CURCNTR(pipe), cntl);
6453 I915_WRITE(CURBASE(pipe), base);
6461 int pipe = intel_crtc->pipe;
6465 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6475 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6480 I915_WRITE(CURBASE_IVB(pipe), base);
6490 int pipe = intel_crtc->pipe;
6531 I915_WRITE(CURPOS_IVB(pipe), pos);
6534 I915_WRITE(CURPOS(pipe), pos);
6616 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6705 /* VESA 640x480x72Hz mode to set on the pipe */
6859 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6896 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6904 intel_wait_for_vblank(dev, intel_crtc->pipe);
6941 /* Returns the clock of the currently programmed mode of the given pipe. */
6946 int pipe = intel_crtc->pipe;
6947 u32 dpll = I915_READ(DPLL(pipe));
6952 fp = I915_READ(FP0(pipe));
6954 fp = I915_READ(FP1(pipe));
6993 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7030 /** Returns the currently programmed mode of the given pipe. */
7067 int pipe = intel_crtc->pipe;
7068 int dpll_reg = DPLL(pipe);
7081 assert_panel_unlocked(dev_priv, pipe);
7085 intel_wait_for_vblank(dev, pipe);
7110 int pipe = intel_crtc->pipe;
7111 int dpll_reg = DPLL(pipe);
7116 assert_panel_unlocked(dev_priv, pipe);
7121 intel_wait_for_vblank(dev, pipe);
7236 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7240 drm_vblank_put(dev, intel_crtc->pipe);
7250 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7253 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7409 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7412 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7453 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7456 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7568 ret = drm_vblank_get(dev, intel_crtc->pipe);
7577 drm_vblank_put(dev, intel_crtc->pipe);
7624 drm_vblank_put(dev, intel_crtc->pipe);
7685 * This function copies the stage display pipe configuration to the real one.
7793 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7794 context, pipe_name(crtc->pipe));
7797 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7861 pipe_config->cpu_transcoder = (enum transcoder)to_intel_crtc(crtc)->pipe;
7919 DRM_ERROR("loop in pipe configuration computation");
7930 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7940 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7965 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7970 1 << connector->new_encoder->new_crtc->pipe;
7981 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7985 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
8004 *disable_pipes |= 1 << intel_crtc->pipe;
8011 *prepare_pipes |= 1 << intel_crtc->pipe;
8014 * For simplicity do a full modeset on any pipe where the output routing
8030 *modeset_pipes &= 1 << intel_crtc->pipe;
8031 *prepare_pipes &= 1 << intel_crtc->pipe;
8033 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8063 if (prepare_pipes & (1 << intel_crtc->pipe))
8081 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8101 if (mask & (1 <<(_intel_crtc)->pipe)) \
8231 enum pipe pipe, tracked_pipe;
8261 active = encoder->get_hw_state(encoder, &pipe);
8270 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8271 if (active && pipe != tracked_pipe)
8272 DRM_ERROR("active encoder's pipe doesn't match"
8274 tracked_pipe, pipe);
8319 /* hw state is inconsistent with the pipe A quirk */
8320 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8325 enum pipe pipe;
8329 encoder->get_hw_state(encoder, &pipe))
8339 DRM_DEBUG_KMS("pipe state doesn't match!\n");
8460 /* mode_set/enable/disable functions rely on a correct pipe
8482 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8894 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
8941 static void intel_crtc_init(struct drm_device *dev, int pipe)
8961 intel_crtc->pipe = pipe;
8962 intel_crtc->plane = pipe;
8965 intel_crtc->plane = !pipe;
8968 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8971 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8995 pipe_from_crtc_id->pipe = crtc->pipe;
9433 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9442 DRM_INFO("applying pipe a force quirk\n");
9514 /* HP Mini needs pipe A force quirk (LP: #322104) */
9517 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9520 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9523 /* 830/845 need to leave pipe A & dpll A up */
9645 DRM_DEBUG_KMS("%d display pipe%s available.\n",
9654 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9685 /* We can't just switch on the pipe A, we need to set things up with a
9686 * proper mode and output configuration. As a gross hack, enable pipe A
9687 * by enabling the load detect pipe once. */
9720 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9736 /* We need to sanitize the plane -> pipe mapping first because this will
9738 * that gen4+ has a fixed plane -> pipe mapping. */
9768 crtc->pipe == PIPE_A && !crtc->active) {
9769 /* BIOS forgot to enable pipe A, this mostly happens after
9770 * resume. Force-enable the pipe to fix this, the update_dpms
9771 * call below we restore the pipe to the right state, but leave
9776 /* Adjust the state of the output pipe according to whether we
9784 * functions or because the pipe is force-enabled due to the
9785 * pipe A quirk. */
9813 * encoder is active and trying to read from a pipe) and the
9814 * pipe itself being active. */
9819 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9823 /* Connector is active, but has no active pipe. This is
9833 /* Inconsistent output/port/pipe state happens presumably due to
9864 enum pipe pipe;
9906 pipe = 0;
9908 if (encoder->get_hw_state(encoder, &pipe)) {
9909 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9918 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9922 pipe);
9948 enum pipe pipe;
9962 for_each_pipe(pipe) {
9963 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9985 for_each_pipe(pipe) {
9987 dev_priv->pipe_to_crtc_mapping[pipe];
10115 } pipe[I915_MAX_PIPES];
10190 error->pipe[i].source = I915_READ(PIPESRC(i));
10238 err_printf(m, " CONF: %08x\n", error->pipe[i].conf);