Cross Reference: /solaris-x11-s11/open-src/kernel/i915/src/intel

Lines Matching refs:p2
56 	intel_p2_t	    p2;
91 	.p2 = { .dot_limit = 165000,
104 	.p2 = { .dot_limit = 165000,
117 	.p2 = { .dot_limit = 200000,
130 	.p2 = { .dot_limit = 112000,
144 	.p2 = { .dot_limit = 270000,
160 	.p2 = { .dot_limit = 165000,
173 	.p2 = { .dot_limit = 0,
187 	.p2 = { .dot_limit = 0,
203 	.p2 = { .dot_limit = 200000,
216 	.p2 = { .dot_limit = 112000,
235 	.p2 = { .dot_limit = 225000,
248 	.p2 = { .dot_limit = 225000,
261 	.p2 = { .dot_limit = 225000,
275 	.p2 = { .dot_limit = 225000,
288 	.p2 = { .dot_limit = 225000,
301 	.p2 = { .dot_limit = 270000,
314 	.p2 = { .dot_limit = 270000,
327 	.p2 = { .dot_limit = 270000,
415 	clock->p = clock->p1 * clock->p2;
428 	clock->p = clock->p1 * clock->p2;
499 			clock.p2 = limit->p2.p2_fast;
501 			clock.p2 = limit->p2.p2_slow;
503 		if (target < limit->p2.dot_limit)
504 			clock.p2 = limit->p2.p2_slow;
506 			clock.p2 = limit->p2.p2_fast;
560 			clock.p2 = limit->p2.p2_fast;
562 			clock.p2 = limit->p2.p2_slow;
564 		if (target < limit->p2.dot_limit)
565 			clock.p2 = limit->p2.p2_slow;
567 			clock.p2 = limit->p2.p2_fast;
618 			clock.p2 = limit->p2.p2_fast;
620 			clock.p2 = limit->p2.p2_slow;
622 		if (target < limit->p2.dot_limit)
623 			clock.p2 = limit->p2.p2_slow;
625 			clock.p2 = limit->p2.p2_fast;
665 	u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
678 	n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
685 			for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
686 				if (p2 > 10)
687 					p2 = p2 - 1;
688 				p = p1 * p2;
698 						if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
711 							bestp2 = p2;
723 	best_clock->p2 = bestp2;
4421 	bestp2 = crtc->config.dpll.p2;
4567 	switch (clock->p2) {
4646 		if (clock->p2 == 4)
4881 	 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4914 		intel_crtc->config.dpll.p2 = clock.p2;
5528 	 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5675 	switch (intel_crtc->config.dpll.p2) {
5741 		intel_crtc->config.dpll.p2 = clock.p2;
6975 			clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6979 			clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6998 			clock.p2 = 14;
7014 				clock.p2 = 4;
7016 				clock.p2 = 2;