Cross Reference: /solaris-x11-s11/open-src/kernel/i915/src/intel

Lines Matching refs:m1
55 	intel_range_t   dot, vco, n, m, m1, m2, p, p1;
87         .m1 = { .min = 18, .max = 26 },
100         .m1 = { .min = 18, .max = 26 },
113 	.m1 = { .min = 8, .max = 18 },
126 	.m1 = { .min = 8, .max = 18 },
140 	.m1 = { .min = 17, .max = 23 },
156 	.m1 = { .min = 16, .max = 23 },
169 	.m1 = { .min = 17, .max = 23 },
183 	.m1 = { .min = 17, .max = 23 },
199         .m1 = { .min = 0, .max = 0 },
212         .m1 = { .min = 0, .max = 0 },
231 	.m1 = { .min = 12, .max = 22 },
244 	.m1 = { .min = 12, .max = 22 },
257 	.m1 = { .min = 12, .max = 22 },
271 	.m1 = { .min = 12, .max = 22 },
284 	.m1 = { .min = 12, .max = 22 },
297 	.m1 = { .min = 2, .max = 3 },
310 	.m1 = { .min = 2, .max = 3 },
323 	.m1 = { .min = 2, .max = 3 },
411 /* m1 is reserved as 0 in Pineview, n is a ring counter */
422 	return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
464 	if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
465 		INTELPllInvalid ("m1 out of range\n");
466 	if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
467 		INTELPllInvalid ("m1 <= m2\n");
511 	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
512 	     clock.m1++) {
515 			if (clock.m2 >= clock.m1)
572 	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
573 	     clock.m1++) {
632 		/* based on hardware requirement prefer larger m1,m2 */
633 		for (clock.m1 = limit->m1.max;
634 		     clock.m1 >= limit->m1.min; clock.m1--) {
665 	u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
678 	n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
689 				/* based on hardware requirement, prefer bigger m1,m2 values */
690 				for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
691 					m2 = (((2*(fastclk * p * n / m1 )) +
693 					m = m1 * m2;
708 							bestm1 = m1;
720 	best_clock->m1 = bestm1;
4302 	return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4418 	bestm1 = crtc->config.dpll.m1;
4881 	 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4911 		intel_crtc->config.dpll.m1 = clock.m1;
5528 	 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5738 		intel_crtc->config.dpll.m1 = clock.m1;
6956 	clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;