Lines Matching refs:intel_crtc
732 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
734 return intel_crtc->config.cpu_transcoder;
909 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1397 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1429 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1470 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1478 intel_crtc_to_shared_dpll(intel_crtc));
1874 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1877 int plane = intel_crtc->plane;
1945 intel_crtc->dspaddr_offset =
1949 linear_offset -= intel_crtc->dspaddr_offset;
1951 intel_crtc->dspaddr_offset = linear_offset;
1959 obj->gtt_offset + intel_crtc->dspaddr_offset);
1974 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1977 int plane = intel_crtc->plane;
2038 intel_crtc->dspaddr_offset =
2042 linear_offset -= intel_crtc->dspaddr_offset;
2048 obj->gtt_offset + intel_crtc->dspaddr_offset);
2095 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2096 enum plane plane = intel_crtc->plane;
2103 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2106 if (intel_crtc->active)
2140 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2149 switch (intel_crtc->pipe) {
2169 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2179 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2181 plane_name(intel_crtc->plane),
2210 if (intel_crtc->active && old_fb != fb)
2211 intel_wait_for_vblank(dev, intel_crtc->pipe);
2227 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2228 int pipe = intel_crtc->pipe;
2264 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2266 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2272 struct intel_crtc *pipe_B_crtc =
2274 struct intel_crtc *pipe_C_crtc =
2300 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2301 int pipe = intel_crtc->pipe;
2302 int plane = intel_crtc->plane;
2323 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2402 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2403 int pipe = intel_crtc->pipe;
2421 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2534 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2535 int pipe = intel_crtc->pipe;
2556 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2646 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2648 struct drm_device *dev = intel_crtc->base.dev;
2650 int pipe = intel_crtc->pipe;
2658 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2683 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2685 struct drm_device *dev = intel_crtc->base.dev;
2687 int pipe = intel_crtc->pipe;
2716 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2717 int pipe = intel_crtc->pipe;
2769 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2774 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2893 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2929 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2930 int pipe = intel_crtc->pipe;
2950 ironlake_enable_shared_dpll(intel_crtc);
2958 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
2967 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3014 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3015 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3022 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3027 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3049 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, u32 dpll, u32 fp)
3141 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3190 int pipe = intel_crtc->pipe;
3191 int plane = intel_crtc->plane;
3196 if (intel_crtc->active)
3199 intel_crtc->active = true;
3213 if (intel_crtc->config.has_pch_encoder) {
3217 ironlake_fdi_pll_enable(intel_crtc);
3227 ironlake_pfit_enable(intel_crtc);
3236 intel_crtc->config.has_pch_encoder);
3241 if (intel_crtc->config.has_pch_encoder)
3252 cpt_verify_modeset(dev, intel_crtc->pipe);
3262 intel_wait_for_vblank(dev, intel_crtc->pipe);
3266 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3271 static void hsw_enable_ips(struct intel_crtc *crtc)
3286 static void hsw_disable_ips(struct intel_crtc *crtc)
3305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3307 int pipe = intel_crtc->pipe;
3308 int plane = intel_crtc->plane;
3312 if (intel_crtc->active)
3315 intel_crtc->active = true;
3318 if (intel_crtc->config.has_pch_encoder)
3323 if (intel_crtc->config.has_pch_encoder)
3330 intel_ddi_enable_pipe_clock(intel_crtc);
3332 ironlake_pfit_enable(intel_crtc);
3344 intel_crtc->config.has_pch_encoder);
3349 hsw_enable_ips(intel_crtc);
3351 if (intel_crtc->config.has_pch_encoder)
3369 intel_wait_for_vblank(dev, intel_crtc->pipe);
3372 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3391 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3393 int pipe = intel_crtc->pipe;
3394 int plane = intel_crtc->plane;
3398 if (!intel_crtc->active)
3414 if (intel_crtc->config.has_pch_encoder)
3419 ironlake_pfit_disable(intel_crtc);
3425 if (intel_crtc->config.has_pch_encoder) {
3447 intel_disable_shared_dpll(intel_crtc);
3449 ironlake_fdi_pll_disable(intel_crtc);
3452 intel_crtc->active = false;
3464 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3466 int pipe = intel_crtc->pipe;
3467 int plane = intel_crtc->plane;
3468 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3470 if (!intel_crtc->active)
3483 hsw_disable_ips(intel_crtc);
3489 if (intel_crtc->config.has_pch_encoder)
3495 ironlake_pfit_disable(intel_crtc);
3497 intel_ddi_disable_pipe_clock(intel_crtc);
3503 if (intel_crtc->config.has_pch_encoder) {
3509 intel_crtc->active = false;
3519 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3520 intel_put_shared_dpll(intel_crtc);
3528 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3530 if (!enable && intel_crtc->overlay) {
3531 struct drm_device *dev = intel_crtc->base.dev;
3536 (void) intel_overlay_switch_off(intel_crtc->overlay);
3570 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3598 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3600 int pipe = intel_crtc->pipe;
3601 int plane = intel_crtc->plane;
3605 if (intel_crtc->active)
3608 intel_crtc->active = true;
3627 i9xx_pfit_enable(intel_crtc);
3645 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3647 int pipe = intel_crtc->pipe;
3648 int plane = intel_crtc->plane;
3652 if (intel_crtc->active)
3655 intel_crtc->active = true;
3664 i9xx_pfit_enable(intel_crtc);
3677 intel_crtc_dpms_overlay(intel_crtc, true);
3685 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3704 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3706 int pipe = intel_crtc->pipe;
3707 int plane = intel_crtc->plane;
3709 if (!intel_crtc->active)
3722 intel_crtc_dpms_overlay(intel_crtc, false);
3729 i9xx_pfit_disable(intel_crtc);
3737 intel_crtc->active = false;
3751 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3752 int pipe = intel_crtc->pipe;
3802 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3808 intel_crtc->eld_vld = false;
3949 struct intel_crtc *pipe_B_crtc =
4008 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4011 struct drm_device *dev = intel_crtc->base.dev;
4040 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4041 intel_crtc->pipe, pipe_config);
4058 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4066 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4305 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4363 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4376 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4397 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4405 static void vlv_update_pll(struct intel_crtc *crtc)
4524 static void i9xx_update_pll(struct intel_crtc *crtc,
4624 static void i8xx_update_pll(struct intel_crtc *crtc,
4679 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4681 struct drm_device *dev = intel_crtc->base.dev;
4683 enum pipe pipe = intel_crtc->pipe;
4684 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4686 &intel_crtc->config.adjusted_mode;
4687 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4743 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4782 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4784 struct drm_device *dev = intel_crtc->base.dev;
4790 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4797 if (intel_crtc->config.requested_mode.clock >
4805 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4809 switch (intel_crtc->config.pipe_bpp) {
4826 if (intel_crtc->lowfreq_avail) {
4835 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4840 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4843 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4844 POSTING_READ(PIPECONF(intel_crtc->pipe));
4853 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4854 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4855 int pipe = intel_crtc->pipe;
4856 int plane = intel_crtc->plane;
4885 intel_crtc->config.port_clock,
4887 if (!ok && !intel_crtc->config.clock_set) {
4909 if (!intel_crtc->config.clock_set) {
4910 intel_crtc->config.dpll.n = clock.n;
4911 intel_crtc->config.dpll.m1 = clock.m1;
4912 intel_crtc->config.dpll.m2 = clock.m2;
4913 intel_crtc->config.dpll.p1 = clock.p1;
4914 intel_crtc->config.dpll.p2 = clock.p2;
4918 i8xx_update_pll(intel_crtc,
4922 vlv_update_pll(intel_crtc);
4924 i9xx_update_pll(intel_crtc,
4938 intel_set_pipe_timings(intel_crtc);
4948 i9xx_set_pipeconf(intel_crtc);
4960 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4987 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5377 int pipe = intel_crtc->pipe;
5382 switch (intel_crtc->config.pipe_bpp) {
5400 if (intel_crtc->config.dither)
5403 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5408 if (intel_crtc->config.limited_color_range)
5426 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5427 int pipe = intel_crtc->pipe;
5437 if (intel_crtc->config.limited_color_range)
5461 if (intel_crtc->config.limited_color_range)
5472 if (intel_crtc->config.limited_color_range)
5482 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5483 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5488 if (intel_crtc->config.dither)
5491 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5499 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5500 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5572 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5574 struct drm_device *dev = intel_crtc->base.dev;
5577 switch (intel_crtc->pipe) {
5581 if (intel_crtc->config.fdi_lanes > 2) {
5613 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5617 struct drm_crtc *crtc = &intel_crtc->base;
5646 } else if (intel_crtc->config.sdvo_tv_clock)
5649 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5662 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5667 if (intel_crtc->config.has_dp_encoder)
5671 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5673 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5675 switch (intel_crtc->config.dpll.p2) {
5704 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5705 int pipe = intel_crtc->pipe;
5706 int plane = intel_crtc->plane;
5731 if (!ok && !intel_crtc->config.clock_set) {
5736 if (!intel_crtc->config.clock_set) {
5737 intel_crtc->config.dpll.n = clock.n;
5738 intel_crtc->config.dpll.m1 = clock.m1;
5739 intel_crtc->config.dpll.m2 = clock.m2;
5740 intel_crtc->config.dpll.p1 = clock.p1;
5741 intel_crtc->config.dpll.p2 = clock.p2;
5748 if (intel_crtc->config.has_pch_encoder) {
5749 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5753 dpll = ironlake_compute_dpll(intel_crtc,
5757 intel_crtc->config.dpll_hw_state.dpll = dpll;
5758 intel_crtc->config.dpll_hw_state.fp0 = fp;
5760 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5762 intel_crtc->config.dpll_hw_state.fp1 = fp;
5764 pll = intel_get_shared_dpll(intel_crtc, dpll, fp);
5771 intel_put_shared_dpll(intel_crtc);
5773 if (intel_crtc->config.has_dp_encoder)
5774 intel_dp_set_m_n(intel_crtc);
5781 intel_crtc->lowfreq_avail = true;
5783 intel_crtc->lowfreq_avail = false;
5785 if (intel_crtc->config.has_pch_encoder) {
5786 pll = intel_crtc_to_shared_dpll(intel_crtc);
5812 intel_set_pipe_timings(intel_crtc);
5814 if (intel_crtc->config.has_pch_encoder) {
5815 intel_cpu_transcoder_set_m_n(intel_crtc,
5816 &intel_crtc->config.fdi_m_n);
5820 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5835 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5851 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5875 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5933 struct intel_crtc *crtc;
5935 list_for_each_entry(crtc, struct intel_crtc, &dev->mode_config.crtc_list, base.head) {
5953 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5954 int plane = intel_crtc->plane;
5963 if (intel_crtc->config.has_dp_encoder)
5964 intel_dp_set_m_n(intel_crtc);
5966 intel_crtc->lowfreq_avail = false;
5968 intel_set_pipe_timings(intel_crtc);
5970 if (intel_crtc->config.has_pch_encoder) {
5971 intel_cpu_transcoder_set_m_n(intel_crtc,
5972 &intel_crtc->config.fdi_m_n);
5990 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6070 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6072 &intel_crtc->config.adjusted_mode;
6073 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6074 int pipe = intel_crtc->pipe;
6177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6219 intel_crtc->eld_vld = true;
6362 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6363 enum pipe pipe = intel_crtc->pipe;
6369 if (!crtc->enabled || !intel_crtc->active)
6382 if (intel_crtc->config.ips_enabled &&
6385 hsw_disable_ips(intel_crtc);
6391 (intel_crtc->lut_r[i] << 16) |
6392 (intel_crtc->lut_g[i] << 8) |
6393 intel_crtc->lut_b[i]);
6397 hsw_enable_ips(intel_crtc);
6404 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6408 if (intel_crtc->cursor_visible == visible)
6427 intel_crtc->cursor_visible = visible;
6434 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6435 int pipe = intel_crtc->pipe;
6438 if (intel_crtc->cursor_visible != visible) {
6450 intel_crtc->cursor_visible = visible;
6460 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6461 int pipe = intel_crtc->pipe;
6464 if (intel_crtc->cursor_visible != visible) {
6477 intel_crtc->cursor_visible = visible;
6489 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6490 int pipe = intel_crtc->pipe;
6491 int x = intel_crtc->cursor_x;
6492 int y = intel_crtc->cursor_y;
6499 base = intel_crtc->cursor_addr;
6509 if (x + intel_crtc->cursor_width < 0)
6518 if (y + intel_crtc->cursor_height < 0)
6527 if (!visible && !intel_crtc->cursor_visible)
6549 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6616 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6629 if (intel_crtc->cursor_bo) {
6631 if (intel_crtc->cursor_bo != obj)
6632 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6634 i915_gem_object_unpin(intel_crtc->cursor_bo);
6635 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6640 intel_crtc->cursor_addr = addr;
6641 intel_crtc->cursor_bo = obj;
6642 intel_crtc->cursor_width = (int16_t)width;
6643 intel_crtc->cursor_height = (int16_t)height;
6645 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6659 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6661 intel_crtc->cursor_x = (int16_t)x;
6662 intel_crtc->cursor_y = (int16_t)y;
6664 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6673 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6675 intel_crtc->lut_r[regno] = red >> 8;
6676 intel_crtc->lut_g[regno] = green >> 8;
6677 intel_crtc->lut_b[regno] = blue >> 8;
6683 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6685 *red = intel_crtc->lut_r[regno] << 8;
6686 *green = intel_crtc->lut_g[regno] << 8;
6687 *blue = intel_crtc->lut_b[regno] << 8;
6694 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6697 intel_crtc->lut_r[i] = red[i] >> 8;
6698 intel_crtc->lut_g[i] = green[i] >> 8;
6699 intel_crtc->lut_b[i] = blue[i] >> 8;
6803 struct intel_crtc *intel_crtc;
6867 intel_crtc = to_intel_crtc(crtc);
6904 intel_wait_for_vblank(dev, intel_crtc->pipe);
6945 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6946 int pipe = intel_crtc->pipe;
7035 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7036 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7066 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7067 int pipe = intel_crtc->pipe;
7097 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7109 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7110 int pipe = intel_crtc->pipe;
7172 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7179 work = intel_crtc->unpin_work;
7180 intel_crtc->unpin_work = NULL;
7192 kfree(intel_crtc, sizeof (struct intel_crtc));
7218 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7223 if (intel_crtc == NULL)
7227 work = intel_crtc->unpin_work;
7233 intel_crtc->unpin_work = NULL;
7236 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7240 drm_vblank_put(dev, intel_crtc->pipe);
7269 struct intel_crtc *intel_crtc =
7278 if (intel_crtc->unpin_work)
7279 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7283 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7287 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7298 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7314 if (intel_crtc->plane)
7321 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7323 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7326 intel_mark_page_flip_active(intel_crtc);
7342 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7355 if (intel_crtc->plane)
7362 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7364 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7367 intel_mark_page_flip_active(intel_crtc);
7383 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7401 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7404 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7412 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7415 intel_mark_page_flip_active(intel_crtc);
7431 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7445 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7447 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7453 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7456 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7459 intel_mark_page_flip_active(intel_crtc);
7481 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7490 switch(intel_crtc->plane) {
7512 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7515 intel_mark_page_flip_active(intel_crtc);
7541 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7568 ret = drm_vblank_get(dev, intel_crtc->pipe);
7574 if (intel_crtc->unpin_work) {
7577 drm_vblank_put(dev, intel_crtc->pipe);
7582 intel_crtc->unpin_work = work;
7585 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7599 atomic_inc(&intel_crtc->unpin_work_count);
7600 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7613 atomic_dec(&intel_crtc->unpin_work_count);
7621 intel_crtc->unpin_work = NULL;
7624 drm_vblank_put(dev, intel_crtc->pipe);
7730 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7789 static void intel_dump_pipe_config(struct intel_crtc *crtc,
7945 struct intel_crtc *intel_crtc;
7989 list_for_each_entry(intel_crtc, struct intel_crtc, &dev->mode_config.crtc_list,
7994 if (!intel_crtc->base.enabled)
7999 if (encoder->new_crtc == intel_crtc)
8004 *disable_pipes |= 1 << intel_crtc->pipe;
8009 intel_crtc = to_intel_crtc(crtc);
8011 *prepare_pipes |= 1 << intel_crtc->pipe;
8030 *modeset_pipes &= 1 << intel_crtc->pipe;
8031 *prepare_pipes &= 1 << intel_crtc->pipe;
8053 struct intel_crtc *intel_crtc;
8061 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8063 if (prepare_pipes & (1 << intel_crtc->pipe))
8070 list_for_each_entry(intel_crtc, struct intel_crtc, &dev->mode_config.crtc_list,
8072 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8079 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8081 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8098 list_for_each_entry((_intel_crtc), struct intel_crtc, \
8283 struct intel_crtc *crtc;
8287 list_for_each_entry(crtc, struct intel_crtc, &dev->mode_config.crtc_list,
8352 struct intel_crtc *crtc;
8378 list_for_each_entry(crtc, struct intel_crtc, &dev->mode_config.crtc_list,
8415 struct intel_crtc *intel_crtc;
8447 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8448 intel_crtc_disable(&intel_crtc->base);
8450 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8451 if (intel_crtc->base.enabled)
8452 dev_priv->display.crtc_disable(&intel_crtc->base);
8475 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8476 ret = intel_crtc_mode_set(&intel_crtc->base,
8483 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8484 dev_priv->display.crtc_enable(&intel_crtc->base);
8888 struct intel_crtc *crtc;
8892 list_for_each_entry(crtc, struct intel_crtc, &dev->mode_config.crtc_list, base.head) {
8944 struct intel_crtc *intel_crtc;
8947 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8948 if (intel_crtc == NULL)
8951 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8953 (void) drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8955 intel_crtc->lut_r[i] = (u8) i;
8956 intel_crtc->lut_g[i] = (u8) i;
8957 intel_crtc->lut_b[i] = (u8) i;
8961 intel_crtc->pipe = pipe;
8962 intel_crtc->plane = pipe;
8965 intel_crtc->plane = !pipe;
8969 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8970 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8971 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8973 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8981 struct intel_crtc *crtc;
9707 intel_check_plane_mapping(struct intel_crtc *crtc)
9726 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9865 struct intel_crtc *crtc;
9870 list_for_each_entry(crtc, struct intel_crtc, &dev->mode_config.crtc_list,
9893 list_for_each_entry(crtc, struct intel_crtc, &dev->mode_config.crtc_list,
9950 struct intel_crtc *crtc;
10019 struct intel_crtc *intel_crtc;
10041 intel_crtc = to_intel_crtc(crtc);