Lines Matching refs:enabled
885 static const char *state_string(bool enabled)
887 return enabled ? "on" : "off";
994 /* ILK FDI PLL is always enabled */
1157 bool enabled;
1165 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1167 if(!enabled)
1176 bool enabled;
1180 enabled = !!(val & TRANS_ENABLE);
1181 if(enabled)
1256 DRM_ERROR("PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1269 DRM_ERROR("PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1290 DRM_ERROR("PCH VGA enabled on transcoder %c, should be disabled\n",
1296 DRM_ERROR("PCH LVDS enabled on transcoder %c, should be disabled\n",
1311 * protect mechanism may be enabled.
1394 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1476 /* Make sure PCH DPLL is enabled */
1606 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1639 /* if driving the PCH, we need FDI enabled */
1697 * Plane regs are double buffered, going from enabled->disabled needs a
1723 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2258 /* IVB wants error correction enabled */
2266 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2280 * with all lanes. Note that we don't care about enabled pipes without
2281 * an enabled pch encoder.
2943 /* XXX: pch pll's can be enabled any time before we enable the PCH
3075 /* Only want to check enabled timings first */
3194 WARN_ON(!crtc->enabled);
3231 * clocks enabled
3256 * outputs) where an enabled pipe still completes any pageflip right
3279 * We guarantee that the plane is enabled by calling intel_enable_ips
3310 WARN_ON(!crtc->enabled);
3336 * clocks enabled
3363 * outputs) where an enabled pipe still completes any pageflip right
3551 * enabled.
3603 WARN_ON(!crtc->enabled);
3650 WARN_ON(!crtc->enabled);
3671 /* The fixup needs to happen before cursor is enabled */
3747 bool enabled)
3763 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3764 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3767 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3768 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3804 /* crtc should still be enabled when we disable it. */
3805 WARN_ON(!crtc->enabled);
3840 if (crtc->enabled)
3892 DRM_ERROR("encoder not enabled\n");
3900 if (!crtc->enabled)
3901 DRM_ERROR("crtc not enabled\n");
3924 /* Only need to change hw state when actually enabled */
3978 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4440 /* Set idtafcrecal before PLL is enabled */
4616 * DPLL is enabled and the clocks are stable.
4672 * DPLL is enabled and the clocks are stable.
5800 * DPLL is enabled and the clocks are stable.
5936 if (!crtc->base.enabled)
6369 if (!crtc->enabled || !intel_crtc->active)
6380 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6498 if (on && crtc->enabled && crtc->fb) {
6849 if (!possible_crtc->enabled) {
7994 if (!intel_crtc->base.enabled)
8010 if (crtc->enabled)
8072 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8229 bool enabled = false;
8246 enabled = true;
8250 if (!!encoder->base.crtc != enabled)
8251 DRM_ERROR("encoder's enabled state mismatch "
8253 !!encoder->base.crtc, enabled);
8289 bool enabled = false;
8297 if (crtc->active && !crtc->base.enabled)
8298 DRM_ERROR("active crtc, but not enabled in sw tracking\n");
8304 enabled = true;
8312 if (enabled != crtc->base.enabled)
8313 DRM_ERROR("crtc's computed enabled state doesn't match tracked enabled state "
8314 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8380 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8389 DRM_DEBUG_KMS("pll enabled crtcs mismatch (expected %i, found %i)\n",
8451 if (intel_crtc->base.enabled)
8499 if (ret && crtc->enabled) {
8702 /* Update crtc of enabled connectors. */
8873 /* PCH refclock must be enabled first */
9433 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9764 crtc->base.enabled = false;
9780 if (crtc->active != crtc->base.enabled) {
9784 * functions or because the pipe is force-enabled due to the
9788 crtc->base.enabled ? "enabled" : "disabled",
9789 crtc->active ? "enabled" : "disabled");
9791 crtc->base.enabled = crtc->active;
9856 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9877 crtc->base.enabled = crtc->active;
9881 crtc->active ? "enabled" : "disabled");
9921 encoder->base.crtc ? "enabled" : "disabled",
9938 connector->base.encoder ? "enabled" : "disabled");
9974 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);