Lines Matching refs:crtc
40 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
41 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
331 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
334 struct drm_device *dev = crtc->dev;
337 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
355 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
357 struct drm_device *dev = crtc->dev;
360 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
365 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
366 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
368 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
376 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
378 struct drm_device *dev = crtc->dev;
382 limit = intel_ironlake_limit(crtc, refclk);
384 limit = intel_g4x_limit(crtc);
386 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
391 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
393 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
398 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
403 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
436 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
438 struct drm_device *dev = crtc->dev;
441 for_each_encoder_on_crtc(dev, crtc, encoder)
484 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
488 struct drm_device *dev = crtc->dev;
492 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
545 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
549 struct drm_device *dev = crtc->dev;
553 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
604 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
608 struct drm_device *dev = crtc->dev;
616 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
661 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
731 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
732 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
909 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
911 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
913 if (crtc->config.shared_dpll < 0)
916 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1397 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1399 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1400 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1413 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1415 crtc->base.base.id);
1429 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1431 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1432 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1446 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1448 crtc->base.base.id);
1469 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1470 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1509 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1869 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1872 struct drm_device *dev = crtc->dev;
1874 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1969 static int ironlake_update_plane(struct drm_crtc *crtc,
1972 struct drm_device *dev = crtc->dev;
1974 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2062 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2065 struct drm_device *dev = crtc->dev;
2070 intel_increase_pllclock(crtc);
2072 return dev_priv->display.update_plane(crtc, fb, x, y);
2078 struct drm_crtc *crtc;
2090 * don't try to grab a crtc mutex before the
2094 list_for_each_entry(crtc, struct drm_crtc, &dev->mode_config.crtc_list, head) {
2095 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2102 list_for_each_entry(crtc, struct drm_crtc, &dev->mode_config.crtc_list, head) {
2103 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2105 mutex_lock(&crtc->mutex);
2107 dev_priv->display.update_plane(crtc, crtc->fb,
2108 crtc->x, crtc->y);
2109 mutex_unlock(&crtc->mutex);
2136 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2138 struct drm_device *dev = crtc->dev;
2140 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2164 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2167 struct drm_device *dev = crtc->dev;
2169 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2180 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2196 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2204 old_fb = crtc->fb;
2205 crtc->fb = fb;
2206 crtc->x = x;
2207 crtc->y = y;
2218 intel_crtc_update_sarea_pos(crtc, x, y);
2223 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2225 struct drm_device *dev = crtc->dev;
2227 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2296 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2298 struct drm_device *dev = crtc->dev;
2300 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2398 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2400 struct drm_device *dev = crtc->dev;
2402 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2530 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2532 struct drm_device *dev = crtc->dev;
2534 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2712 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2714 struct drm_device *dev = crtc->dev;
2716 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2765 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2767 struct drm_device *dev = crtc->dev;
2769 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2778 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2784 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2789 struct drm_device *dev = crtc->dev;
2792 if (crtc->fb == NULL)
2798 !intel_crtc_has_pending_flip(crtc));
2801 intel_finish_fb(crtc->fb);
2806 static void lpt_program_iclkip(struct drm_crtc *crtc)
2808 struct drm_device *dev = crtc->dev;
2827 if (crtc->mode.clock == 20000) {
2833 * but the crtc->mode.clock in in KHz. To get the divisors,
2842 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2858 crtc->mode.clock,
2893 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2896 struct drm_device *dev = crtc->base.dev;
2898 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2925 static void ironlake_pch_enable(struct drm_crtc *crtc)
2927 struct drm_device *dev = crtc->dev;
2929 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2941 dev_priv->display.fdi_link_train(crtc);
2969 intel_fdi_normal_train(crtc);
2973 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2974 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2985 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2987 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2990 switch (intel_trans_dp_port_sel(crtc)) {
3010 static void lpt_pch_enable(struct drm_crtc *crtc)
3012 struct drm_device *dev = crtc->dev;
3014 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3019 lpt_program_iclkip(crtc);
3027 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3029 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3046 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3049 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, u32 dpll, u32 fp)
3051 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3052 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3057 crtc->base.base.id, pll->name);
3058 intel_put_shared_dpll(crtc);
3063 i = (enum intel_dpll_id)crtc->pipe;
3067 crtc->base.base.id, pll->name);
3082 crtc->base.base.id,
3094 crtc->base.base.id, pll->name);
3102 crtc->config.shared_dpll = i;
3104 pipe_name(crtc->pipe));
3107 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3141 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3143 struct drm_device *dev = crtc->base.dev;
3145 int pipe = crtc->pipe;
3147 if (crtc->config.pch_pfit.size) {
3157 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3158 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3162 static void intel_enable_planes(struct drm_crtc *crtc)
3164 struct drm_device *dev = crtc->dev;
3165 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3173 static void intel_disable_planes(struct drm_crtc *crtc)
3175 struct drm_device *dev = crtc->dev;
3176 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3184 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3186 struct drm_device *dev = crtc->dev;
3188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3194 WARN_ON(!crtc->enabled);
3206 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3223 for_each_encoder_on_crtc(dev, crtc, encoder)
3233 intel_crtc_load_lut(crtc);
3238 intel_enable_planes(crtc);
3239 intel_crtc_update_cursor(crtc, true);
3242 ironlake_pch_enable(crtc);
3248 for_each_encoder_on_crtc(dev, crtc, encoder)
3266 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3268 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3271 static void hsw_enable_ips(struct intel_crtc *crtc)
3273 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3275 if (!crtc->config.ips_enabled)
3282 assert_plane_enabled(dev_priv, crtc->plane);
3286 static void hsw_disable_ips(struct intel_crtc *crtc)
3288 struct drm_device *dev = crtc->base.dev;
3291 if (!crtc->config.ips_enabled)
3294 assert_plane_enabled(dev_priv, crtc->plane);
3298 intel_wait_for_vblank(dev, crtc->pipe);
3301 static void haswell_crtc_enable(struct drm_crtc *crtc)
3303 struct drm_device *dev = crtc->dev;
3305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3310 WARN_ON(!crtc->enabled);
3324 dev_priv->display.fdi_link_train(crtc);
3326 for_each_encoder_on_crtc(dev, crtc, encoder)
3338 intel_crtc_load_lut(crtc);
3340 intel_ddi_set_pipe_settings(crtc);
3341 intel_ddi_enable_transcoder_func(crtc);
3346 intel_enable_planes(crtc);
3347 intel_crtc_update_cursor(crtc, true);
3352 lpt_pch_enable(crtc);
3358 for_each_encoder_on_crtc(dev, crtc, encoder)
3372 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3374 struct drm_device *dev = crtc->base.dev;
3376 int pipe = crtc->pipe;
3380 if (crtc->config.pch_pfit.size) {
3387 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3389 struct drm_device *dev = crtc->dev;
3391 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3401 for_each_encoder_on_crtc(dev, crtc, encoder)
3404 intel_crtc_wait_for_pending_flips(crtc);
3410 intel_crtc_update_cursor(crtc, false);
3411 intel_disable_planes(crtc);
3421 for_each_encoder_on_crtc(dev, crtc, encoder)
3426 ironlake_fdi_disable(crtc);
3460 static void haswell_crtc_disable(struct drm_crtc *crtc)
3462 struct drm_device *dev = crtc->dev;
3464 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3473 for_each_encoder_on_crtc(dev, crtc, encoder)
3476 intel_crtc_wait_for_pending_flips(crtc);
3485 intel_crtc_update_cursor(crtc, false);
3486 intel_disable_planes(crtc);
3499 for_each_encoder_on_crtc(dev, crtc, encoder)
3506 intel_ddi_fdi_disable(crtc);
3517 static void ironlake_crtc_off(struct drm_crtc *crtc)
3519 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3523 static void haswell_crtc_off(struct drm_crtc *crtc)
3525 intel_ddi_put_crtc_pll(crtc);
3570 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3572 struct drm_device *dev = crtc->base.dev;
3574 struct intel_crtc_config *pipe_config = &crtc->config;
3576 if (!crtc->config.gmch_pfit.control)
3584 assert_pipe_disabled(dev_priv, crtc->pipe);
3591 I915_WRITE(BCLRPAT(crtc->pipe), 0);
3594 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3596 struct drm_device *dev = crtc->dev;
3598 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3603 WARN_ON(!crtc->enabled);
3613 for_each_encoder_on_crtc(dev, crtc, encoder)
3619 for_each_encoder_on_crtc(dev, crtc, encoder)
3624 for_each_encoder_on_crtc(dev, crtc, encoder)
3629 intel_crtc_load_lut(crtc);
3633 intel_enable_planes(crtc);
3634 intel_crtc_update_cursor(crtc, true);
3641 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3643 struct drm_device *dev = crtc->dev;
3645 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3650 WARN_ON(!crtc->enabled);
3660 for_each_encoder_on_crtc(dev, crtc, encoder)
3666 intel_crtc_load_lut(crtc);
3670 intel_enable_planes(crtc);
3674 intel_crtc_update_cursor(crtc, true);
3681 for_each_encoder_on_crtc(dev, crtc, encoder)
3685 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3687 struct drm_device *dev = crtc->base.dev;
3690 if (!crtc->config.gmch_pfit.control)
3693 assert_pipe_disabled(dev_priv, crtc->pipe);
3700 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3702 struct drm_device *dev = crtc->dev;
3704 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3712 for_each_encoder_on_crtc(dev, crtc, encoder)
3716 intel_crtc_wait_for_pending_flips(crtc);
3723 intel_crtc_update_cursor(crtc, false);
3724 intel_disable_planes(crtc);
3731 for_each_encoder_on_crtc(dev, crtc, encoder)
3742 static void i9xx_crtc_off(struct drm_crtc *crtc)
3746 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3749 struct drm_device *dev = crtc->dev;
3751 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3763 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3764 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3767 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3768 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3779 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3781 struct drm_device *dev = crtc->dev;
3786 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3790 dev_priv->display.crtc_enable(crtc);
3792 dev_priv->display.crtc_disable(crtc);
3794 intel_crtc_update_sarea(crtc, enable);
3797 static void intel_crtc_disable(struct drm_crtc *crtc)
3799 struct drm_device *dev = crtc->dev;
3802 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3804 /* crtc should still be enabled when we disable it. */
3805 WARN_ON(!crtc->enabled);
3807 dev_priv->display.crtc_disable(crtc);
3809 intel_crtc_update_sarea(crtc, false);
3810 dev_priv->display.off(crtc);
3812 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3813 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3815 if (crtc->fb) {
3817 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3819 crtc->fb = NULL;
3824 if (!connector->encoder || !connector->encoder->crtc)
3827 if (connector->encoder->crtc != crtc)
3837 struct drm_crtc *crtc;
3839 list_for_each_entry(crtc, struct drm_crtc, &dev->mode_config.crtc_list, head) {
3840 if (crtc->enabled)
3841 intel_crtc_disable(crtc);
3861 intel_crtc_update_dpms(encoder->base.crtc);
3865 intel_crtc_update_dpms(encoder->base.crtc);
3875 struct drm_crtc *crtc;
3893 if (!encoder->base.crtc) {
3894 DRM_ERROR("crtc is NULL");
3898 crtc = encoder->base.crtc;
3900 if (!crtc->enabled)
3901 DRM_ERROR("crtc not enabled\n");
3902 if (!to_intel_crtc(crtc)->active)
3903 DRM_ERROR("crtc not active\n");
3904 if (pipe != to_intel_crtc(crtc)->pipe)
3925 if (encoder->base.crtc)
4058 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4062 hsw_crtc_supports_ips(crtc) &&
4066 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4069 struct drm_device *dev = crtc->base.dev;
4080 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4101 hsw_compute_ips_config(crtc, pipe_config);
4106 pipe_config->shared_dpll = crtc->config.shared_dpll;
4109 return ironlake_fdi_compute_config(crtc, pipe_config);
4250 static int vlv_get_refclk(struct drm_crtc *crtc)
4253 struct drm_device *dev = crtc->dev;
4259 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4261 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4266 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4273 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4275 struct drm_device *dev = crtc->dev;
4280 refclk = vlv_get_refclk(crtc);
4281 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4305 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4308 struct drm_device *dev = crtc->base.dev;
4310 int pipe = crtc->pipe;
4314 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4318 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4325 crtc->lowfreq_avail = false;
4326 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4329 crtc->lowfreq_avail = true;
4363 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4366 struct drm_device *dev = crtc->base.dev;
4368 int pipe = crtc->pipe;
4376 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4379 struct drm_device *dev = crtc->base.dev;
4381 int pipe = crtc->pipe;
4382 enum transcoder transcoder = crtc->config.cpu_transcoder;
4397 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4399 if (crtc->config.has_pch_encoder)
4400 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4402 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4405 static void vlv_update_pll(struct intel_crtc *crtc)
4407 struct drm_device *dev = crtc->base.dev;
4410 int pipe = crtc->pipe;
4417 bestn = crtc->config.dpll.n;
4418 bestm1 = crtc->config.dpll.m1;
4419 bestm2 = crtc->config.dpll.m2;
4420 bestp1 = crtc->config.dpll.p1;
4421 bestp2 = crtc->config.dpll.p2;
4458 if (crtc->config.port_clock == 162000 ||
4459 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4460 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4467 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4468 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4488 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4489 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4495 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4513 dpll_md = (crtc->config.pixel_multiplier - 1)
4518 if (crtc->config.has_dp_encoder)
4519 intel_dp_set_m_n(crtc);
4524 static void i9xx_update_pll(struct intel_crtc *crtc,
4528 struct drm_device *dev = crtc->base.dev;
4531 int pipe = crtc->pipe;
4534 struct dpll *clock = &crtc->config.dpll;
4536 i9xx_update_pll_dividers(crtc, reduced_clock);
4538 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4539 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4543 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4549 dpll |= (crtc->config.pixel_multiplier - 1)
4556 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4584 if (crtc->config.sdvo_tv_clock)
4586 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4597 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4601 if (crtc->config.has_dp_encoder)
4602 intel_dp_set_m_n(crtc);
4611 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4624 static void i8xx_update_pll(struct intel_crtc *crtc,
4628 struct drm_device *dev = crtc->base.dev;
4631 int pipe = crtc->pipe;
4633 struct dpll *clock = &crtc->config.dpll;
4635 i9xx_update_pll_dividers(crtc, reduced_clock);
4639 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4650 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4661 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4743 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4746 struct drm_device *dev = crtc->base.dev;
4777 tmp = I915_READ(PIPESRC(crtc->pipe));
4847 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4851 struct drm_device *dev = crtc->dev;
4853 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4866 for_each_encoder_on_crtc(dev, crtc, encoder) {
4876 refclk = i9xx_get_refclk(crtc, num_connectors);
4883 limit = intel_limit(crtc, refclk);
4884 ok = dev_priv->display.find_dpll(limit, crtc,
4893 intel_crtc_update_cursor(crtc, true);
4903 dev_priv->display.find_dpll(limit, crtc,
4953 ret = intel_pipe_set_base(crtc, x, y, fb);
4960 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4963 struct drm_device *dev = crtc->base.dev;
4973 if (crtc->pipe != PIPE_B)
4976 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4987 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4990 struct drm_device *dev = crtc->base.dev;
4994 pipe_config->cpu_transcoder = (enum transcoder)crtc->pipe;
4997 tmp = I915_READ(PIPECONF(crtc->pipe));
5001 intel_get_pipe_timings(crtc, pipe_config);
5003 i9xx_get_pfit_config(crtc, pipe_config);
5006 tmp = I915_READ(DPLL_MD(crtc->pipe));
5011 tmp = I915_READ(DPLL(crtc->pipe));
5347 static int ironlake_get_refclk(struct drm_crtc *crtc)
5349 struct drm_device *dev = crtc->dev;
5355 for_each_encoder_on_crtc(dev, crtc, encoder) {
5373 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5375 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5422 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5424 struct drm_device *dev = crtc->dev;
5426 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5479 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5481 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5482 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5503 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5508 struct drm_device *dev = crtc->dev;
5515 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5523 refclk = ironlake_get_refclk(crtc);
5530 limit = intel_limit(crtc, refclk);
5531 ret = dev_priv->display.find_dpll(limit, crtc,
5532 to_intel_crtc(crtc)->config.port_clock,
5545 dev_priv->display.find_dpll(limit, crtc,
5617 struct drm_crtc *crtc = &intel_crtc->base;
5618 struct drm_device *dev = crtc->dev;
5625 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5698 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5702 struct drm_device *dev = crtc->dev;
5704 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5716 for_each_encoder_on_crtc(dev, crtc, encoder) {
5729 ok = ironlake_compute_clocks(crtc, &clock,
5745 intel_crtc_update_cursor(crtc, true);
5776 for_each_encoder_on_crtc(dev, crtc, encoder)
5822 ironlake_set_pipeconf(crtc);
5828 ret = intel_pipe_set_base(crtc, x, y, fb);
5835 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5838 struct drm_device *dev = crtc->base.dev;
5851 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5854 struct drm_device *dev = crtc->base.dev;
5858 tmp = I915_READ(PF_CTL(crtc->pipe));
5861 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5862 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5869 PF_PIPE_SEL_IVB(crtc->pipe));
5870 DRM_DEBUG("PF_CTL(crtc->pipe) 0x%x", tmp);
5875 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5878 struct drm_device *dev = crtc->base.dev;
5882 pipe_config->cpu_transcoder = (enum transcoder)crtc->pipe;
5885 tmp = I915_READ(PIPECONF(crtc->pipe));
5889 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5895 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5899 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5906 pipe_config->shared_dpll = (enum intel_dpll_id)crtc->pipe;
5909 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5923 intel_get_pipe_timings(crtc, pipe_config);
5925 ironlake_get_pfit_config(crtc, pipe_config);
5933 struct intel_crtc *crtc;
5935 list_for_each_entry(crtc, struct intel_crtc, &dev->mode_config.crtc_list, base.head) {
5936 if (!crtc->base.enabled)
5939 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5940 crtc->config.cpu_transcoder != TRANSCODER_EDP)
5947 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5951 struct drm_device *dev = crtc->dev;
5953 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5957 if (!intel_ddi_pll_mode_set(crtc))
5961 intel_crtc_update_cursor(crtc, true);
5975 haswell_set_pipeconf(crtc);
5977 intel_set_pipe_csc(crtc);
5983 ret = intel_pipe_set_base(crtc, x, y, fb);
5990 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5993 struct drm_device *dev = crtc->base.dev;
5998 pipe_config->cpu_transcoder = (enum transcoder)crtc->pipe;
6019 if (trans_edp_pipe == crtc->pipe)
6045 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6048 intel_get_pipe_timings(crtc, pipe_config);
6050 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6052 ironlake_get_pfit_config(crtc, pipe_config);
6054 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6062 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6066 struct drm_device *dev = crtc->dev;
6070 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6079 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6086 for_each_encoder_on_crtc(dev, crtc, encoder) {
6132 struct drm_crtc *crtc)
6172 struct drm_crtc *crtc)
6176 struct drm_device *dev = crtc->dev;
6177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6181 int pipe = to_intel_crtc(crtc)->pipe;
6221 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6259 struct drm_crtc *crtc)
6270 int pipe = to_intel_crtc(crtc)->pipe;
6299 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6336 struct drm_crtc *crtc = encoder->crtc;
6354 dev_priv->display.write_eld(connector, crtc);
6358 void intel_crtc_load_lut(struct drm_crtc *crtc)
6360 struct drm_device *dev = crtc->dev;
6362 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6369 if (!crtc->enabled || !intel_crtc->active)
6400 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6402 struct drm_device *dev = crtc->dev;
6404 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6430 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6432 struct drm_device *dev = crtc->dev;
6434 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6456 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6458 struct drm_device *dev = crtc->dev;
6460 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6484 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6487 struct drm_device *dev = crtc->dev;
6489 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6498 if (on && crtc->enabled && crtc->fb) {
6500 if (x > (int) crtc->fb->width)
6503 if (y > (int) crtc->fb->height)
6532 ivb_update_cursor(crtc, base);
6536 i845_update_cursor(crtc, base);
6538 i9xx_update_cursor(crtc, base);
6542 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6547 struct drm_device *dev = crtc->dev;
6549 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6645 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6657 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6659 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6664 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6670 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6673 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6680 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6683 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6690 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6694 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6702 intel_crtc_load_lut(crtc);
6808 struct drm_crtc *crtc = NULL;
6820 * - if the connector already has an assigned crtc, use it (but make
6823 * - try to find the first unused crtc that can drive this connector,
6828 if (encoder->crtc) {
6829 crtc = encoder->crtc;
6831 mutex_lock(&crtc->mutex);
6833 /* Make sure the crtc and connector are running */
6837 /* Make sure the crtc and connector are running */
6850 crtc = possible_crtc;
6858 if (!crtc) {
6863 mutex_lock(&crtc->mutex);
6864 intel_encoder->new_crtc = to_intel_crtc(crtc);
6867 intel_crtc = to_intel_crtc(crtc);
6891 mutex_unlock(&crtc->mutex);
6895 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6899 mutex_unlock(&crtc->mutex);
6914 struct drm_crtc *crtc = encoder->crtc;
6923 intel_set_mode(crtc, NULL, 0, 0, NULL);
6930 mutex_unlock(&crtc->mutex);
6934 /* Switch crtc and encoder back off if necessary */
6938 mutex_unlock(&crtc->mutex);
6942 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6945 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7032 struct drm_crtc *crtc)
7035 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7047 mode->clock = intel_crtc_clock_get(dev, crtc);
7062 void intel_increase_pllclock(struct drm_crtc *crtc)
7064 struct drm_device *dev = crtc->dev;
7066 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7093 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7095 struct drm_device *dev = crtc->dev;
7097 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7135 struct drm_crtc *crtc;
7140 list_for_each_entry(crtc, struct drm_crtc, &dev->mode_config.crtc_list, head) {
7141 if (!crtc->fb)
7144 intel_decrease_pllclock(crtc);
7152 struct drm_crtc *crtc;
7157 list_for_each_entry(crtc, struct drm_crtc, &dev->mode_config.crtc_list, head) {
7158 if (!crtc->fb)
7161 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7164 intel_increase_pllclock(crtc);
7170 static void intel_crtc_destroy(struct drm_crtc *crtc)
7172 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7173 struct drm_device *dev = crtc->dev;
7188 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7190 drm_crtc_cleanup(crtc);
7199 struct drm_device *dev = work->crtc->dev;
7209 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7210 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7215 struct drm_crtc *crtc)
7218 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7253 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7255 do_intel_finish_page_flip(dev, crtc);
7261 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7263 do_intel_finish_page_flip(dev, crtc);
7293 struct drm_crtc *crtc,
7298 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7337 struct drm_crtc *crtc,
7342 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7378 struct drm_crtc *crtc,
7383 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7426 struct drm_crtc *crtc,
7431 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7476 struct drm_crtc *crtc,
7481 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7526 struct drm_crtc *crtc,
7533 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7537 struct drm_device *dev = crtc->dev;
7539 struct drm_framebuffer *old_fb = crtc->fb;
7541 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7547 if (fb->pixel_format != crtc->fb->pixel_format)
7555 (fb->offsets[0] != crtc->fb->offsets[0] ||
7556 fb->pitches[0] != crtc->fb->pitches[0]))
7564 work->crtc = crtc;
7579 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7594 crtc->fb = fb;
7602 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7614 crtc->fb = old_fb;
7637 struct drm_crtc *crtc)
7643 ASSERT(crtc);
7645 dev = crtc->dev;
7648 if (tmp == crtc)
7678 to_intel_crtc(encoder->base.crtc);
7699 encoder->base.crtc = &encoder->new_crtc->base;
7730 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7734 struct drm_device *dev = crtc->base.dev;
7780 connector->new_encoder->new_crtc != crtc)
7789 static void intel_dump_pipe_config(struct intel_crtc *crtc,
7793 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7794 context, pipe_name(crtc->pipe));
7819 static bool check_encoder_cloning(struct drm_crtc *crtc)
7825 list_for_each_entry(encoder, struct intel_encoder, &crtc->dev->mode_config.encoder_list,
7827 if (&encoder->new_crtc->base != crtc)
7839 intel_modeset_pipe_config(struct drm_crtc *crtc,
7843 struct drm_device *dev = crtc->dev;
7850 if (!check_encoder_cloning(crtc)) {
7861 pipe_config->cpu_transcoder = (enum transcoder)to_intel_crtc(crtc)->pipe;
7867 * after encoders and crtc also have had their say. */
7868 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7885 if (&encoder->new_crtc->base != crtc)
7911 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
7940 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7942 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7946 struct drm_device *dev = crtc->dev;
7963 tmp_crtc = connector->base.encoder->crtc;
7975 if (encoder->base.crtc == &encoder->new_crtc->base)
7978 if (encoder->base.crtc) {
7979 tmp_crtc = encoder->base.crtc;
8009 intel_crtc = to_intel_crtc(crtc);
8010 if (crtc->enabled)
8037 static bool intel_crtc_in_use(struct drm_crtc *crtc)
8040 struct drm_device *dev = crtc->dev;
8043 if (encoder->crtc == crtc)
8058 if (!intel_encoder->base.crtc)
8061 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8076 if (!connector->encoder || !connector->encoder->crtc)
8079 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8237 if (&encoder->new_crtc->base != encoder->base.crtc)
8238 DRM_ERROR("encoder's stage crtc doesn't match current crtc\n");
8239 if (encoder->connectors_active && !encoder->base.crtc)
8240 DRM_ERROR("encoder's active_connectors set, but no crtc\n");
8250 if (!!encoder->base.crtc != enabled)
8253 !!encoder->base.crtc, enabled);
8254 if (active && !encoder->base.crtc)
8255 DRM_ERROR("active encoder with no crtc\n");
8267 if (!encoder->base.crtc)
8270 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8283 struct intel_crtc *crtc;
8287 list_for_each_entry(crtc, struct intel_crtc, &dev->mode_config.crtc_list,
8295 crtc->base.base.id);
8297 if (crtc->active && !crtc->base.enabled)
8298 DRM_ERROR("active crtc, but not enabled in sw tracking\n");
8302 if (encoder->base.crtc != &crtc->base)
8309 if (active != crtc->active)
8310 DRM_ERROR("crtc's computed active state doesn't match tracked active state "
8311 "(expected %i, found %i)\n", active, crtc->active);
8312 if (enabled != crtc->base.enabled)
8313 DRM_ERROR("crtc's computed enabled state doesn't match tracked enabled state "
8314 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8316 active = dev_priv->display.get_pipe_config(crtc,
8320 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8321 active = crtc->active;
8326 if (encoder->base.crtc != &crtc->base)
8333 if(crtc->active != active)
8334 DRM_ERROR("crtc active state doesn't match with hw state "
8335 "(expected %i, found %i)\n", crtc->active, active);
8338 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8340 intel_dump_pipe_config(crtc, &pipe_config,
8342 intel_dump_pipe_config(crtc, &crtc->config,
8352 struct intel_crtc *crtc;
8378 list_for_each_entry(crtc, struct intel_crtc, &dev->mode_config.crtc_list,
8380 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8382 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8407 static int __intel_set_mode(struct drm_crtc *crtc,
8411 struct drm_device *dev = crtc->dev;
8424 intel_modeset_affected_pipes(crtc, &modeset_pipes,
8427 *saved_hwmode = crtc->hwmode;
8428 *saved_mode = crtc->mode;
8431 * crtcs, we don't keep track of the new mode for more than one crtc.
8436 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8443 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8455 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8459 crtc->mode = *mode;
8462 to_intel_crtc(crtc)->config = *pipe_config;
8488 crtc->hwmode = pipe_config->adjusted_mode;
8494 drm_calc_timestamping_constants(crtc);
8499 if (ret && crtc->enabled) {
8500 crtc->hwmode = *saved_hwmode;
8501 crtc->mode = *saved_mode;
8511 int intel_set_mode(struct drm_crtc *crtc,
8517 ret = __intel_set_mode(crtc, mode, x, y, fb);
8520 intel_modeset_check_state(crtc->dev);
8525 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8527 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8567 config->save_encoder_crtcs[count++] = encoder->crtc;
8611 set->connectors[i]->encoder->crtc == set->crtc &&
8627 } else if (set->crtc->fb != set->fb) {
8629 if (set->crtc->fb == NULL) {
8630 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8635 set->crtc->fb->pixel_format) {
8642 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8645 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8647 drm_mode_debug_printmodeline(&set->crtc->mode);
8664 /* The upper layers ensure that we either disabl a crtc or have a list
8681 /* If we disable the crtc, disable all its connectors. Also, if
8682 * the connector is on the changing crtc but not on the new
8686 connector->base.encoder->crtc == set->crtc) {
8702 /* Update crtc of enabled connectors. */
8709 new_crtc = connector->new_encoder->base.crtc;
8713 new_crtc = set->crtc;
8743 /* Only now check for crtc changes so we don't miss encoders
8745 if (&encoder->new_crtc->base != encoder->base.crtc) {
8746 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8763 BUG_ON(!set->crtc);
8764 BUG_ON(!set->crtc->helper_private);
8772 set->crtc->base.id, set->fb->base.id,
8775 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8778 dev = set->crtc->dev;
8789 save_set.crtc = set->crtc;
8790 save_set.mode = &set->crtc->mode;
8791 save_set.x = set->crtc->x;
8792 save_set.y = set->crtc->y;
8793 save_set.fb = set->crtc->fb;
8812 ret = intel_set_mode(set->crtc, set->mode,
8815 intel_crtc_wait_for_pending_flips(set->crtc);
8817 ret = intel_pipe_set_base(set->crtc,
8823 set->crtc->base.id, ret);
8829 intel_set_mode(save_set.crtc, save_set.mode,
8888 struct intel_crtc *crtc;
8892 list_for_each_entry(crtc, struct intel_crtc, &dev->mode_config.crtc_list, base.head) {
8893 if (intel_crtc_to_shared_dpll(crtc) == pll)
8894 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
8981 struct intel_crtc *crtc;
8994 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8995 pipe_from_crtc_id->pipe = crtc->pipe;
9676 connector->encoder->base.crtc = NULL;
9707 intel_check_plane_mapping(struct intel_crtc *crtc)
9709 struct drm_device *dev = crtc->base.dev;
9716 reg = DSPCNTR(!crtc->plane);
9720 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9726 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9728 struct drm_device *dev = crtc->base.dev;
9733 reg = PIPECONF(crtc->config.cpu_transcoder);
9737 * disable the crtc (and hence change the state) if it is wrong. Note
9739 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9744 crtc->base.base.id);
9749 plane = crtc->plane;
9750 crtc->plane = !plane;
9751 dev_priv->display.crtc_disable(&crtc->base);
9752 crtc->plane = plane;
9757 if (connector->encoder->base.crtc != &crtc->base)
9763 WARN_ON(crtc->active);
9764 crtc->base.enabled = false;
9768 crtc->pipe == PIPE_A && !crtc->active) {
9778 intel_crtc_update_dpms(&crtc->base);
9780 if (crtc->active != crtc->base.enabled) {
9787 crtc->base.base.id,
9788 crtc->base.enabled ? "enabled" : "disabled",
9789 crtc->active ? "enabled" : "disabled");
9791 crtc->base.enabled = crtc->active;
9794 * crtc links if something is active, this means the
9795 * crtc is now deactivated. Break the links. connector
9798 WARN_ON(crtc->active);
9800 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9802 encoder->base.crtc = NULL;
9812 /* We need to check both for a crtc link (meaning that the
9815 bool has_active_crtc = encoder->base.crtc &&
9816 to_intel_crtc(encoder->base.crtc)->active;
9826 if (encoder->base.crtc) {
9847 * the crtc fixup. */
9865 struct intel_crtc *crtc;
9870 list_for_each_entry(crtc, struct intel_crtc, &dev->mode_config.crtc_list,
9872 (void) memset(&crtc->config, 0, sizeof(crtc->config));
9874 crtc->active = dev_priv->display.get_pipe_config(crtc,
9875 &crtc->config);
9877 crtc->base.enabled = crtc->active;
9880 crtc->base.base.id,
9881 crtc->active ? "enabled" : "disabled");
9893 list_for_each_entry(crtc, struct intel_crtc, &dev->mode_config.crtc_list,
9895 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9909 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9910 encoder->base.crtc = &crtc->base;
9912 encoder->get_config(encoder, &crtc->config);
9914 encoder->base.crtc = NULL;
9921 encoder->base.crtc ? "enabled" : "disabled",
9950 struct intel_crtc *crtc;
9963 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9964 intel_sanitize_crtc(crtc);
9965 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
9986 struct drm_crtc *crtc =
9989 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9990 crtc->fb);
10017 struct drm_crtc *crtc;
10036 list_for_each_entry(crtc, struct drm_crtc, &dev->mode_config.crtc_list, head) {
10038 if (!crtc->fb)
10041 intel_crtc = to_intel_crtc(crtc);
10042 intel_increase_pllclock(crtc);