Lines Matching refs:config
734 return intel_crtc->config.cpu_transcoder;
913 if (crtc->config.shared_dpll < 0)
916 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
2266 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2323 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2421 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2556 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2658 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2898 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2958 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3015 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3046 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3102 crtc->config.shared_dpll = i;
3107 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3147 if (crtc->config.pch_pfit.size) {
3157 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3158 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3213 if (intel_crtc->config.has_pch_encoder) {
3236 intel_crtc->config.has_pch_encoder);
3241 if (intel_crtc->config.has_pch_encoder)
3275 if (!crtc->config.ips_enabled)
3291 if (!crtc->config.ips_enabled)
3318 if (intel_crtc->config.has_pch_encoder)
3323 if (intel_crtc->config.has_pch_encoder)
3344 intel_crtc->config.has_pch_encoder);
3351 if (intel_crtc->config.has_pch_encoder)
3380 if (crtc->config.pch_pfit.size) {
3414 if (intel_crtc->config.has_pch_encoder)
3425 if (intel_crtc->config.has_pch_encoder) {
3468 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3489 if (intel_crtc->config.has_pch_encoder)
3503 if (intel_crtc->config.has_pch_encoder) {
3574 struct intel_crtc_config *pipe_config = &crtc->config;
3576 if (!crtc->config.gmch_pfit.control)
3690 if (!crtc->config.gmch_pfit.control)
3952 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3955 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3980 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3987 pipe_B_crtc->config.fdi_lanes <= 2) {
3989 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4106 pipe_config->shared_dpll = crtc->config.shared_dpll;
4314 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4318 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4382 enum transcoder transcoder = crtc->config.cpu_transcoder;
4399 if (crtc->config.has_pch_encoder)
4400 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4402 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4417 bestn = crtc->config.dpll.n;
4418 bestm1 = crtc->config.dpll.m1;
4419 bestm2 = crtc->config.dpll.m2;
4420 bestp1 = crtc->config.dpll.p1;
4421 bestp2 = crtc->config.dpll.p2;
4458 if (crtc->config.port_clock == 162000 ||
4513 dpll_md = (crtc->config.pixel_multiplier - 1)
4518 if (crtc->config.has_dp_encoder)
4534 struct dpll *clock = &crtc->config.dpll;
4549 dpll |= (crtc->config.pixel_multiplier - 1)
4584 if (crtc->config.sdvo_tv_clock)
4601 if (crtc->config.has_dp_encoder)
4611 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4633 struct dpll *clock = &crtc->config.dpll;
4684 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4686 &intel_crtc->config.adjusted_mode;
4687 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4797 if (intel_crtc->config.requested_mode.clock >
4805 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4809 switch (intel_crtc->config.pipe_bpp) {
4835 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4840 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4854 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4885 intel_crtc->config.port_clock,
4887 if (!ok && !intel_crtc->config.clock_set) {
4909 if (!intel_crtc->config.clock_set) {
4910 intel_crtc->config.dpll.n = clock.n;
4911 intel_crtc->config.dpll.m1 = clock.m1;
4912 intel_crtc->config.dpll.m2 = clock.m2;
4913 intel_crtc->config.dpll.p1 = clock.p1;
4914 intel_crtc->config.dpll.p2 = clock.p2;
5037 /* We need to take the global config into account */
5382 switch (intel_crtc->config.pipe_bpp) {
5400 if (intel_crtc->config.dither)
5403 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5408 if (intel_crtc->config.limited_color_range)
5437 if (intel_crtc->config.limited_color_range)
5461 if (intel_crtc->config.limited_color_range)
5472 if (intel_crtc->config.limited_color_range)
5483 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5488 if (intel_crtc->config.dither)
5491 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5532 to_intel_crtc(crtc)->config.port_clock,
5581 if (intel_crtc->config.fdi_lanes > 2) {
5646 } else if (intel_crtc->config.sdvo_tv_clock)
5649 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5662 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5667 if (intel_crtc->config.has_dp_encoder)
5671 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5673 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5675 switch (intel_crtc->config.dpll.p2) {
5731 if (!ok && !intel_crtc->config.clock_set) {
5736 if (!intel_crtc->config.clock_set) {
5737 intel_crtc->config.dpll.n = clock.n;
5738 intel_crtc->config.dpll.m1 = clock.m1;
5739 intel_crtc->config.dpll.m2 = clock.m2;
5740 intel_crtc->config.dpll.p1 = clock.p1;
5741 intel_crtc->config.dpll.p2 = clock.p2;
5748 if (intel_crtc->config.has_pch_encoder) {
5749 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5757 intel_crtc->config.dpll_hw_state.dpll = dpll;
5758 intel_crtc->config.dpll_hw_state.fp0 = fp;
5760 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5762 intel_crtc->config.dpll_hw_state.fp1 = fp;
5773 if (intel_crtc->config.has_dp_encoder)
5785 if (intel_crtc->config.has_pch_encoder) {
5814 if (intel_crtc->config.has_pch_encoder) {
5816 &intel_crtc->config.fdi_m_n);
5939 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5940 crtc->config.cpu_transcoder != TRANSCODER_EDP)
5963 if (intel_crtc->config.has_dp_encoder)
5970 if (intel_crtc->config.has_pch_encoder) {
5972 &intel_crtc->config.fdi_m_n);
6072 &intel_crtc->config.adjusted_mode;
6073 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6382 if (intel_crtc->config.ips_enabled &&
7036 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7793 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7890 DRM_DEBUG_KMS("Encoder config failure\n");
8338 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8342 intel_dump_pipe_config(crtc, &crtc->config,
8461 * config. */
8462 to_intel_crtc(crtc)->config = *pipe_config;
8532 static void intel_set_config_free(struct drm_device *dev, struct intel_set_config *config)
8534 if (!config)
8537 kfree(config->save_connector_encoders, dev->mode_config.num_connector * sizeof(struct drm_encoder *));
8538 kfree(config->save_encoder_crtcs, dev->mode_config.num_encoder * sizeof(struct drm_crtc *));
8539 kfree(config, sizeof(*config));
8543 struct intel_set_config *config)
8549 config->save_encoder_crtcs =
8552 if (!config->save_encoder_crtcs)
8555 config->save_connector_encoders =
8558 if (!config->save_connector_encoders)
8567 config->save_encoder_crtcs[count++] = encoder->crtc;
8572 config->save_connector_encoders[count++] = connector->encoder;
8579 struct intel_set_config *config)
8588 to_intel_crtc(config->save_encoder_crtcs[count++]);
8594 to_intel_encoder(config->save_connector_encoders[count++]);
8620 struct intel_set_config *config)
8626 config->mode_changed = true;
8631 config->mode_changed = true;
8633 config->mode_changed = true;
8636 config->mode_changed = true;
8638 config->fb_changed = true;
8643 config->fb_changed = true;
8649 config->mode_changed = true;
8656 struct intel_set_config *config)
8697 config->mode_changed = true;
8747 config->mode_changed = true;
8759 struct intel_set_config *config;
8781 config = kzalloc(sizeof(*config), GFP_KERNEL);
8782 if (!config)
8785 ret = intel_set_config_save_state(dev, config);
8799 intel_set_config_compute_mode_changes(set, config);
8801 ret = intel_modeset_stage_output_state(dev, set, config);
8805 if (config->mode_changed) {
8814 } else if (config->fb_changed) {
8825 intel_set_config_restore_state(dev, config);
8827 /* Try to restore the config */
8828 if (config->mode_changed &&
8831 DRM_ERROR("failed to restore config after modeset failure\n");
8835 intel_set_config_free(dev, config);
9733 reg = PIPECONF(crtc->config.cpu_transcoder);
9872 (void) memset(&crtc->config, 0, sizeof(crtc->config));
9875 &crtc->config);
9912 encoder->get_config(encoder, &crtc->config);
9965 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");