Lines Matching refs:bpp
4044 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4804 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5597 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5604 u32 bps = target_clock * bpp * 21 / 20;
6736 intel_framebuffer_pitch_for_width(int width, int bpp)
6738 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6743 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6745 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6752 int depth, int bpp)
6758 intel_framebuffer_size_for_mode(mode, bpp));
6767 bpp);
6768 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7707 int bpp = pipe_config->pipe_bpp;
7709 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7715 connector->base.display_info.bpc * 3 < bpp) {
7716 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7717 bpp, connector->base.display_info.bpc*3);
7721 /* Clamp bpp to 8 on screens without EDID 1.4 */
7722 if (connector->base.display_info.bpc == 0 && bpp > 24) {
7723 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7724 bpp);
7736 int bpp;
7740 bpp = 8*3; /* since we go through a colormap */
7748 bpp = 6*3; /* min is 18bpp */
7757 bpp = 8*3;
7766 bpp = 10*3;
7774 pipe_config->pipe_bpp = bpp;
7776 /* Clamp display bpp to EDID value */
7786 return bpp;
7797 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7866 * source plane bpp so that dithering can be selected on mismatches
7930 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",