Lines Matching refs:bit
782 /* Wait for vblank interrupt bit to set */
795 * spinning on the vblank interrupt status bit, since we won't actually
799 * wait for the pipe register state bit to turn off
850 u32 bit;
855 bit = SDE_PORTB_HOTPLUG;
858 bit = SDE_PORTC_HOTPLUG;
861 bit = SDE_PORTD_HOTPLUG;
869 bit = SDE_PORTB_HOTPLUG_CPT;
872 bit = SDE_PORTC_HOTPLUG_CPT;
875 bit = SDE_PORTD_HOTPLUG_CPT;
882 return I915_READ(SDEISR) & bit;
1485 /* Workaround: Set the timing override bit before enabling the
1533 /* Workaround: set timing override bit. */
1574 /* Workaround: Clear the timing override chicken bit again. */
1593 /* Workaround: clear timing override bit. */
2309 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2406 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2538 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2826 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3281 * for a vblank, so all we need to do here is to enable the IPS bit. */
7956 * bit set at most. */
8432 * Hence simply check whether any bit is set in modeset_pipes in all the
10211 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to