Cross Reference: /solaris-x11-s11/open-src/kernel/i915/src/intel

Lines Matching defs:transcoder
728 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
809 	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
951 	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1055 	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1182 		DRM_ERROR("transcoder assertion failed, should be off on pipe %c but is still active\n",
1256 		DRM_ERROR("PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1261 		DRM_ERROR("IBX PCH dp port still using transcoder B\n");
1269 		DRM_ERROR("PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1274 		DRM_ERROR("IBX PCH hdmi port still using transcoder B\n");
1290 		DRM_ERROR("PCH VGA enabled on transcoder %c, should be disabled\n",
1296 		DRM_ERROR("PCH LVDS enabled on transcoder %c, should be disabled\n",
1394  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1395  * drives the transcoder clock.
1486 		 * pch transcoder. */
1499 		 * make the BPC in transcoder be consistent with
1518 		DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1522 				      enum transcoder cpu_transcoder)
1549 		DRM_ERROR("Failed to enable PCH transcoder\n");
1558 	/* FDI relies on the transcoder */
1569 	/* wait for PCH transcoder off, transcoder state */
1571 		DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1589 	/* wait for PCH transcoder off, transcoder state */
1591 		DRM_ERROR("Failed to disable PCH transcoder\n");
1616  	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1671 	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2898 	enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2921  *   - update transcoder timings
2923  *   - transcoder
2944 	 * transcoder, and we actually should do this to not upset any PCH
2945 	 * transcoder that already use the clock when we share it.
2965 	/* set transcoder timing */
3015 	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3021 	/* Set transcoder timing. */
3468 	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4382 	enum transcoder transcoder = crtc->config.cpu_transcoder;
4385 		I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4386 		I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4387 		I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4388 		I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4684 	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4748 	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4994 	pipe_config->cpu_transcoder = (enum transcoder)crtc->pipe;
5483 	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5840 	enum transcoder transcoder = pipe_config->cpu_transcoder;
5842 	pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5843 	pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5844 	pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5846 	pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5847 	pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5882 	pipe_config->cpu_transcoder = (enum transcoder)crtc->pipe;
5998 	pipe_config->cpu_transcoder = (enum transcoder)crtc->pipe;
6006 			DRM_ERROR("unknown pipe linked to edp transcoder\n");
6032 	 * Haswell has only FDI/PCH transcoder A. It is which is connected to
6034 	 * the PCH transcoder is on.
7036 	enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7861 	pipe_config->cpu_transcoder = (enum transcoder)to_intel_crtc(crtc)->pipe;
8891 	/* Make sure no transcoder isn't still depending on us. */
10128 		enum transcoder cpu_transcoder;
10138 	} transcoder[4];
10197 		enum transcoder cpu_transcoder = transcoders[i];
10199 		error->transcoder[i].cpu_transcoder = cpu_transcoder;
10201 		error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10202 		error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10203 		error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10204 		error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10205 		error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10206 		error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10207 		error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
10261 		err_printf(m, "  CPU transcoder: %c\n",
10262 			   transcoder_name(error->transcoder[i].cpu_transcoder));
10263 		err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
10264 		err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
10265 		err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
10266 		err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
10267 		err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
10268 		err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
10269 		err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);