Lines Matching defs:refclk
265 /* LVDS 100mhz refclk limits. */
332 int refclk)
339 if (refclk == 100000)
344 if (refclk == 100000)
376 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
382 limit = intel_ironlake_limit(crtc, refclk);
412 static void pineview_clock(int refclk, intel_clock_t *clock)
416 clock->vco = refclk * clock->m / clock->n;
425 static void i9xx_clock(int refclk, intel_clock_t *clock)
429 clock->vco = refclk * clock->m / (clock->n + 2);
450 * Returns whether the given set of divisors are valid for a given refclk with
485 int target, int refclk, intel_clock_t *match_clock,
523 i9xx_clock(refclk, &clock);
546 int target, int refclk, intel_clock_t *match_clock,
582 pineview_clock(refclk, &clock);
605 int target, int refclk, intel_clock_t *match_clock,
641 i9xx_clock(refclk, &clock);
662 int target, int refclk, intel_clock_t *match_clock,
682 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
683 updrate = refclk / n;
692 refclk) / (2*refclk));
1160 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1168 DRM_ERROR("PCH refclk assertion failure, should be active but is disabled\n");
4255 int refclk = 27000; /* for DP & HDMI */
4260 refclk = 96000;
4263 refclk = 100000;
4265 refclk = 96000;
4267 refclk = 100000;
4269 return refclk;
4277 int refclk;
4280 refclk = vlv_get_refclk(crtc);
4283 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4285 refclk / 1000);
4287 refclk = 96000;
4289 refclk = 48000;
4292 return refclk;
4857 int refclk, num_connectors = 0;
4876 refclk = i9xx_get_refclk(crtc, num_connectors);
4880 * refclk, or FALSE. The returned values represent the clock equation:
4883 limit = intel_limit(crtc, refclk);
4886 refclk, NULL, &clock);
4905 refclk, &clock,
5511 int refclk;
5523 refclk = ironlake_get_refclk(crtc);
5527 * refclk, or FALSE. The returned values represent the clock equation:
5530 limit = intel_limit(crtc, refclk);
5533 refclk, NULL, clock);
5547 refclk, clock,