Lines Matching defs:pll
921 struct intel_shared_dpll *pll,
932 if (!pll) {
937 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
940 pll->name, state_string(state), state_string(cur_state));
1400 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1404 if (pll == NULL) {
1405 DRM_ERROR("pll is NULL");
1408 if (pll->refcount == 0) {
1409 DRM_ERROR("pll refcount equal to 0");
1414 pll->name, pll->active, pll->on,
1417 if (pll->active++) {
1418 WARN_ON(!pll->on);
1419 assert_shared_dpll_enabled(dev_priv, pll);
1422 WARN_ON(pll->on);
1424 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1425 pll->enable(dev_priv, pll);
1426 pll->on = true;
1432 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1436 if (pll == NULL) {
1437 DRM_ERROR("pll is NULL");
1441 if (pll->refcount == 0) {
1442 DRM_ERROR("pll refcount equal to 0");
1447 pll->name, pll->active, pll->on,
1450 if ((pll->active == 0)) {
1451 assert_shared_dpll_disabled(dev_priv, pll);
1455 assert_shared_dpll_enabled(dev_priv, pll);
1456 WARN_ON(!pll->on);
1457 if (--pll->active)
1460 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1461 pll->disable(dev_priv, pll);
1462 pll->on = false;
2943 /* XXX: pch pll's can be enabled any time before we enable the PCH
2948 * unconditionally resets the pll - we need that to have the right LVDS
3029 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3031 if (pll == NULL)
3034 if (pll->refcount == 0) {
3039 if (--pll->refcount == 0) {
3040 WARN_ON(pll->on);
3041 WARN_ON(pll->active);
3042 if (pll->on || pll->active)
3052 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3055 if (pll) {
3057 crtc->base.base.id, pll->name);
3064 pll = &dev_priv->shared_dplls[i];
3067 crtc->base.base.id, pll->name);
3073 pll = &dev_priv->shared_dplls[i];
3076 if (pll->refcount == 0)
3079 if ((dpll & 0x7fffffff) == (I915_READ(PCH_DPLL(pll->id)) & 0x7fffffff) &&
3080 fp == I915_READ(PCH_FP0(pll->id))) {
3083 pll->name, pll->refcount, pll->active);
3091 pll = &dev_priv->shared_dplls[i];
3092 if (pll->refcount == 0) {
3094 crtc->base.base.id, pll->name);
3103 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3106 if (pll->active == 0) {
3107 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3108 sizeof(pll->hw_state));
3110 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3111 WARN_ON(pll->on);
3112 assert_shared_dpll_disabled(dev_priv, pll);
3115 I915_WRITE(PCH_DPLL(pll->id), dpll & ~DPLL_VCO_ENABLE);
3116 POSTING_READ(PCH_DPLL(pll->id));
3119 I915_WRITE(PCH_FP0(pll->id), fp);
3120 I915_WRITE(PCH_DPLL(pll->id), dpll & ~DPLL_VCO_ENABLE);
3122 pll->refcount++;
3124 return pll;
5713 struct intel_shared_dpll *pll;
5764 pll = intel_get_shared_dpll(intel_crtc, dpll, fp);
5765 if (pll == NULL) {
5786 pll = intel_crtc_to_shared_dpll(intel_crtc);
5789 * so pll should not be NULL from above call.
5791 BUG_ON(pll == NULL);
5793 I915_WRITE(PCH_DPLL(pll->id), dpll);
5796 POSTING_READ(PCH_DPLL(pll->id));
5804 I915_WRITE(PCH_DPLL(pll->id), dpll);
5807 I915_WRITE(PCH_FP1(pll->id), fp2);
5809 I915_WRITE(PCH_FP1(pll->id), fp);
5891 struct intel_shared_dpll *pll;
5915 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5917 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8357 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8363 DRM_DEBUG_KMS("%s\n", pll->name);
8365 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8367 if(pll->active > pll->refcount)
8368 DRM_DEBUG_KMS("more active pll users than references: %i vs %i\n",
8369 pll->active, pll->refcount);
8370 if(pll->active && !pll->on)
8371 DRM_DEBUG_KMS("pll in active use but not on in sw tracking\n");
8372 if(pll->on && !pll->active)
8373 DRM_DEBUG_KMS("pll in on but not on in use in sw tracking\n");
8374 if(pll->on != active)
8375 DRM_DEBUG_KMS("pll on state mismatch (expected %i, found %i)\n",
8376 pll->on, active);
8380 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8382 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8385 if(pll->active != active_crtcs)
8386 DRM_DEBUG_KMS("pll active crtcs mismatch (expected %i, found %i)\n",
8387 pll->active, active_crtcs);
8388 if(pll->refcount != enabled_crtcs)
8389 DRM_DEBUG_KMS("pll enabled crtcs mismatch (expected %i, found %i)\n",
8390 pll->refcount, enabled_crtcs);
8392 if(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8394 DRM_ERROR("pll hw state mismatch\n");
8855 struct intel_shared_dpll *pll,
8860 val = I915_READ(PCH_DPLL(pll->id));
8862 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
8863 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
8869 struct intel_shared_dpll *pll)
8876 reg = PCH_DPLL(pll->id);
8885 struct intel_shared_dpll *pll)
8893 if (intel_crtc_to_shared_dpll(crtc) == pll)
8897 reg = PCH_DPLL(pll->id);
9889 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9891 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
9892 pll->active = 0;
9895 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9896 pll->active++;
9898 pll->refcount = pll->active;
9901 pll->name, pll->refcount, pll->on);
9969 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9971 if (!pll->on || pll->active)
9974 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
9976 pll->disable(dev_priv, pll);
9977 pll->on = false;