Lines Matching defs:plane
1077 enum plane plane, bool state)
1083 reg = DSPCNTR(plane);
1087 DRM_ERROR("plane %c assertion failure, should be active but is disabled\n",
1088 plane_name(plane));
1107 DRM_ERROR("plane %c assertion failure, should be disabled but not\n",
1119 DRM_ERROR("plane %c assertion failure, should be off on pipe %c but is still active\n",
1309 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1632 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1662 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1701 enum plane plane)
1704 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1706 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1710 * intel_enable_plane - enable a display plane on a given pipe
1712 * @plane: plane to enable
1715 * Enable @plane on @pipe, making sure that @pipe is running first.
1718 enum plane plane, enum pipe pipe)
1726 reg = DSPCNTR(plane);
1732 intel_flush_display_plane(dev_priv, plane);
1737 * intel_disable_plane - disable a display plane
1739 * @plane: plane to disable
1742 * Disable @plane; should be an independent operation.
1745 enum plane plane, enum pipe pipe)
1750 reg = DSPCNTR(plane);
1756 intel_flush_display_plane(dev_priv, plane);
1877 int plane = intel_crtc->plane;
1882 switch (plane) {
1887 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1894 reg = DSPCNTR(plane);
1956 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1958 I915_MODIFY_DISPBASE(DSPSURF(plane),
1960 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1961 I915_WRITE(DSPLINOFF(plane), linear_offset);
1963 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
1977 int plane = intel_crtc->plane;
1982 switch (plane) {
1988 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1995 reg = DSPCNTR(plane);
2046 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2047 I915_MODIFY_DISPBASE(DSPSURF(plane),
2050 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2052 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2053 I915_WRITE(DSPLINOFF(plane), linear_offset);
2096 enum plane plane = intel_crtc->plane;
2098 intel_prepare_page_flip(dev, plane);
2099 intel_finish_page_flip_plane(dev, plane);
2179 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2180 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2181 plane_name(intel_crtc->plane),
2302 int plane = intel_crtc->plane;
2305 /* FDI needs bits from pipe & plane first */
2307 assert_plane_enabled(dev_priv, plane);
3191 int plane = intel_crtc->plane;
3237 intel_enable_plane(dev_priv, plane, pipe);
3278 /* We can only enable IPS after we enable a plane and wait for a vblank.
3279 * We guarantee that the plane is enabled by calling intel_enable_ips
3282 assert_plane_enabled(dev_priv, crtc->plane);
3294 assert_plane_enabled(dev_priv, crtc->plane);
3297 /* We need to wait for a vblank before we can disable the plane. */
3308 int plane = intel_crtc->plane;
3345 intel_enable_plane(dev_priv, plane, pipe);
3394 int plane = intel_crtc->plane;
3407 if (dev_priv->cfb_plane == plane)
3412 intel_disable_plane(dev_priv, plane, pipe);
3467 int plane = intel_crtc->plane;
3479 /* FBC must be disabled before disabling the plane on HSW. */
3480 if (dev_priv->cfb_plane == plane)
3487 intel_disable_plane(dev_priv, plane, pipe);
3548 * cursor plane briefly if not already running after enabling the display
3549 * plane.
3601 int plane = intel_crtc->plane;
3632 intel_enable_plane(dev_priv, plane, pipe);
3648 int plane = intel_crtc->plane;
3669 intel_enable_plane(dev_priv, plane, pipe);
3707 int plane = intel_crtc->plane;
3719 if (dev_priv->cfb_plane == plane)
3725 intel_disable_plane(dev_priv, plane, pipe);
3777 * Sets the power management mode of the pipe and plane.
3812 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4856 int plane = intel_crtc->plane;
4928 /* Set up the display plane register */
4943 I915_WRITE(DSPSIZE(plane),
4946 I915_WRITE(DSPPOS(plane), 0);
4950 I915_WRITE(DSPCNTR(plane), dspcntr);
4951 POSTING_READ(DSPCNTR(plane));
5706 int plane = intel_crtc->plane;
5824 /* Set up the display plane register */
5825 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5826 POSTING_READ(DSPCNTR(plane));
5954 int plane = intel_crtc->plane;
5979 /* Set up the display plane register */
5980 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5981 POSTING_READ(DSPCNTR(plane));
6876 * that the plane may generate whilst we perform load detection.
7258 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7261 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7266 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7270 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7273 /* NB: An MMIO update of the plane base pointer will also
7314 if (intel_crtc->plane)
7321 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7355 if (intel_crtc->plane)
7362 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7401 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7445 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7490 switch(intel_crtc->plane) {
7501 DRM_ERROR("unknown plane in flip command\n");
7865 * plane pixel format and any sink constraints into account. Returns the
7866 * source plane bpp so that dithering can be selected on mismatches
7930 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8482 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8962 intel_crtc->plane = pipe;
8965 intel_crtc->plane = !pipe;
8969 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8970 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9234 /* Reject formats not supported by any plane early. */
9575 /* Disable the VGA plane that we never use */
9716 reg = DSPCNTR(!crtc->plane);
9736 /* We need to sanitize the plane -> pipe mapping first because this will
9738 * that gen4+ has a fixed plane -> pipe mapping. */
9741 bool plane;
9743 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9746 /* Pipe has the wrong plane attached and the plane is active.
9747 * Temporarily change the plane mapping and disable everything
9749 plane = crtc->plane;
9750 crtc->plane = !plane;
9752 crtc->plane = plane;
9856 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9949 struct drm_plane *plane;
9992 list_for_each_entry(plane, struct drm_plane, &dev->mode_config.plane_list, head)
9993 intel_plane_restore(plane);
10125 } plane[I915_MAX_PIPES];
10177 error->plane[i].control = I915_READ(DSPCNTR(i));
10178 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
10180 error->plane[i].size = I915_READ(DSPSIZE(i));
10181 error->plane[i].pos = I915_READ(DSPPOS(i));
10184 error->plane[i].addr = I915_READ(DSPADDR(i));
10186 error->plane[i].surface = I915_READ(DSPSURF(i));
10187 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10241 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10242 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
10244 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
10245 err_printf(m, " POS: %08x\n", error->plane[i].pos);
10248 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
10250 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
10251 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);