Lines Matching defs:on
41 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
434 * Returns whether any output on the specified pipe is of the specified type
474 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
494 * For LVDS just rely on its current settings for dual-channel.
555 * For LVDS just rely on its current settings for dual-channel.
630 /* based on hardware requirement prefer smaller n to precision */
632 /* based on hardware requirement prefer larger m1,m2 */
681 /* based on hardware requirement, prefer smaller n to precision */
689 /* based on hardware requirement, prefer bigger m1,m2 values */
749 * intel_wait_for_vblank - wait for vblank on a given pipe
753 * Wait for vblank to occur on a given pipe. Needed for various bits of
774 * should *not* be performing page flips and thus not waiting on
795 * spinning on the vblank interrupt status bit, since we won't actually
887 return enabled ? "on" : "off";
1058 /* if we need the pipe A quirk it must be always on */
1102 /* Planes are fixed to pipes on ILK+ */
1119 DRM_ERROR("plane %c assertion failure, should be off on pipe %c but is still active\n",
1136 DRM_ERROR("sprite %c assertion failure, should be off on pipe %c but is still active\n",
1143 DRM_ERROR("sprite %c assertion failure, should be off on pipe %c but is still active\n",
1149 DRM_ERROR("sprite %c assertion failure, should be off on pipe %c but is still active\n",
1182 DRM_ERROR("transcoder assertion failed, should be off on pipe %c but is still active\n",
1256 DRM_ERROR("PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1269 DRM_ERROR("PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1290 DRM_ERROR("PCH VGA enabled on transcoder %c, should be disabled\n",
1296 DRM_ERROR("PCH LVDS enabled on transcoder %c, should be disabled\n",
1315 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1365 /* Make sure the pipe isn't still relying on us */
1402 /* PCH PLLs only available on ILK, SNB and IVB */
1413 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1414 pll->name, pll->active, pll->on,
1418 WARN_ON(!pll->on);
1422 WARN_ON(pll->on);
1426 pll->on = true;
1434 /* PCH only available on ILK+ */
1446 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1447 pll->name, pll->active, pll->on,
1456 WARN_ON(!pll->on);
1462 pll->on = false;
1473 /* PCH only available on ILK+ */
1526 /* PCH only available on ILK+ */
1558 /* FDI relies on the transcoder */
1603 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1710 * intel_enable_plane - enable a display plane on a given pipe
1715 * Enable @plane on @pipe, making sure that @pipe is running first.
2122 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2672 /* Enable CPU FDI TX PLL, always on for Ironlake */
3040 WARN_ON(pll->on);
3042 if (pll->on || pll->active)
3111 WARN_ON(pll->on);
3255 * There seems to be a race in PCH platform hw (at least on some
3265 /* IPS only exists on ULT machines and is tied to pipe A. */
3362 * There seems to be a race in PCH platform hw (at least on some
3378 /* To avoid upsetting the power well on haswell only disable the pfit if
3479 /* FBC must be disabled before disabling the plane on HSW. */
3541 /* Let userspace switch the overlay on again. In most cases userspace
3676 /* Give the overlay scaler a chance to enable if it's on this pipe */
3715 /* Give the overlay scaler a chance to disable if it's on this pipe */
3905 DRM_ERROR("encoder active on the wrong pipe\n");
3952 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3955 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3962 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3980 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3989 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4432 /* Disable target IRef on PLL */
4447 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4730 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4794 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
5016 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5119 /* SSC must be turned on before enabling the CPU output */
5121 DRM_DEBUG_KMS("Using SSC on panel\n");
5133 /* Enable CPU source on CPU attached eDP */
5136 DRM_DEBUG_KMS("Using SSC on eDP\n");
5864 /* We currently do not free assignements of panel fitters on
6034 * the PCH transcoder is on.
6216 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6284 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6290 /* operate blindly on all ports */
6295 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6345 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6368 /* The clocks have to be on to load the palette. */
6452 /* and commit changes on next vblank */
6479 /* and commit changes on next vblank */
6483 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6485 bool on)
6498 if (on && crtc->enabled && crtc->fb) {
6669 /** Sets the color ramps on behalf of RandR */
6705 /* VESA 640x480x72Hz mode to set on the pipe */
6821 * sure it's on first)
6877 * We can not rely on the fbcon either being present (we get called
6896 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7023 * i830PllIsValid() because it relies on the xf86_config connector
7408 * untested on non-native modes, so ignore it for now.
7721 /* Clamp bpp to 8 on screens without EDID 1.4 */
7866 * source plane bpp so that dithering can be selected on mismatches
8008 /* set_mode is also used to update properties on life display pipes. */
8014 * For simplicity do a full modeset on any pipe where the output routing
8183 /* pfit ratios are autocomputed by the hw on gen4+ */
8370 if(pll->active && !pll->on)
8371 DRM_DEBUG_KMS("pll in active use but not on in sw tracking\n");
8372 if(pll->on && !pll->active)
8373 DRM_DEBUG_KMS("pll in on but not on in use in sw tracking\n");
8374 if(pll->on != active)
8375 DRM_DEBUG_KMS("pll on state mismatch (expected %i, found %i)\n",
8376 pll->on, active);
8392 if(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8430 /* Hack: Because we don't (yet) support global modeset on multiple
8460 /* mode_set/enable/disable functions rely on a correct pipe
8473 * on the DPLL.
8682 * the connector is on the changing crtc but not on the new
8822 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
8891 /* Make sure no transcoder isn't still depending on us. */
8960 /* Swap pipes & planes for FBC on pre-965 */
9098 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9115 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9133 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9433 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9446 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9493 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9527 /* Lenovo U160 cannot use SSC on LVDS */
9530 /* Sony Vaio Y cannot use SSC on LVDS */
9685 /* We can't just switch on the pipe A, we need to set things up with a
9772 * the required bits on. */
9835 * in our code, like the register restore mess on resume. Clamp
9891 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
9900 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
9901 pll->name, pll->refcount, pll->on);
9971 if (!pll->on || pll->active)
9977 pll->on = false;
10211 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to