Cross Reference: /solaris-x11-s11/open-src/kernel/i915/src/intel

Lines Matching defs:m2
55 	intel_range_t   dot, vco, n, m, m1, m2, p, p1;
88         .m2 = { .min = 6, .max = 16 },
101         .m2 = { .min = 6, .max = 16 },
114 	.m2 = { .min = 3, .max = 7 },
127 	.m2 = { .min = 3, .max = 7 },
141 	.m2 = { .min = 5, .max = 11 },
157 	.m2 = { .min = 5, .max = 11 },
170 	.m2 = { .min = 5, .max = 11 },
184 	.m2 = { .min = 5, .max = 11 },
198 	/* Pineview only has one combined m divider, which we treat as m2. */
200         .m2 = { .min = 0, .max = 254 },
213         .m2 = { .min = 0, .max = 254 },
232 	.m2 = { .min = 5, .max = 9 },
245 	.m2 = { .min = 5, .max = 9 },
258 	.m2 = { .min = 5, .max = 9 },
272 	.m2 = { .min = 5, .max = 9 },
285 	.m2 = { .min = 5, .max = 9 },
298 	.m2 = { .min = 11, .max = 156 },
311 	.m2 = { .min = 11, .max = 156 },
324 	.m2 = { .min = 11, .max = 156 },
414 	clock->m = clock->m2 + 2;
422 	return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
462 	if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
463 		INTELPllInvalid ("m2 out of range\n");
466 	if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
467 		INTELPllInvalid ("m1 <= m2\n");
513 		for (clock.m2 = limit->m2.min;
514 		     clock.m2 <= limit->m2.max; clock.m2++) {
515 			if (clock.m2 >= clock.m1)
574 		for (clock.m2 = limit->m2.min;
575 		     clock.m2 <= limit->m2.max; clock.m2++) {
632 		/* based on hardware requirement prefer larger m1,m2 */
635 			for (clock.m2 = limit->m2.max;
636 			     clock.m2 >= limit->m2.min; clock.m2--) {
665 	u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
678 	n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
689 				/* based on hardware requirement, prefer bigger m1,m2 values */
691 					m2 = (((2*(fastclk * p * n / m1 )) +
693 					m = m1 * m2;
709 							bestm2 = m2;
721 	best_clock->m2 = bestm2;
4297 	return (1 << dpll->n) << 16 | dpll->m2;
4302 	return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4419 	bestm2 = crtc->config.dpll.m2;
4881 	 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4912 		intel_crtc->config.dpll.m2 = clock.m2;
5528 	 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5739 		intel_crtc->config.dpll.m2 = clock.m2;
6959 		clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6962 		clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;