Lines Matching defs:fp
3049 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, u32 dpll, u32 fp)
3080 fp == I915_READ(PCH_FP0(pll->id))) {
3119 I915_WRITE(PCH_FP0(pll->id), fp);
4311 u32 fp, fp2 = 0;
4314 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4318 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4323 I915_WRITE(FP0(pipe), fp);
4331 I915_WRITE(FP1(pipe), fp);
5614 u32 *fp,
5650 *fp |= FP_CB_TUNE;
5709 u32 dpll = 0, fp = 0, fp2 = 0;
5749 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5754 &fp, &reduced_clock,
5758 intel_crtc->config.dpll_hw_state.fp0 = fp;
5762 intel_crtc->config.dpll_hw_state.fp1 = fp;
5764 pll = intel_get_shared_dpll(intel_crtc, dpll, fp);
5809 I915_WRITE(PCH_FP1(pll->id), fp);
6948 u32 fp;
6952 fp = I915_READ(FP0(pipe));
6954 fp = I915_READ(FP1(pipe));
6956 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6958 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6959 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6961 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6962 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;