Cross Reference: /solaris-x11-s11/open-src/kernel/i915/src/intel

Lines Matching defs:error
2258 	/* IVB wants error correction enabled */
2935 	/* Write the TU size bits before fdi link training, so that error
10146 	struct intel_display_error_state *error;
10158 	error = kmalloc(sizeof(*error), GFP_ATOMIC);
10159 	if (error == NULL)
10163 		error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10168 			error->cursor[i].control = I915_READ(CURCNTR(i));
10169 			error->cursor[i].position = I915_READ(CURPOS(i));
10170 			error->cursor[i].base = I915_READ(CURBASE(i));
10172 			error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10173 			error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10174 			error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10177 		error->plane[i].control = I915_READ(DSPCNTR(i));
10178 		error->plane[i].stride = I915_READ(DSPSTRIDE(i));
10180 			error->plane[i].size = I915_READ(DSPSIZE(i));
10181 			error->plane[i].pos = I915_READ(DSPPOS(i));
10184 			error->plane[i].addr = I915_READ(DSPADDR(i));
10186 			error->plane[i].surface = I915_READ(DSPSURF(i));
10187 			error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10190 		error->pipe[i].source = I915_READ(PIPESRC(i));
10192 	error->num_transcoders = INTEL_INFO(dev)->num_pipes;
10194 		error->num_transcoders++; /* Account for eDP. */
10196 	for (i = 0; i < error->num_transcoders; i++) {
10199 		error->transcoder[i].cpu_transcoder = cpu_transcoder;
10201 		error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10202 		error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10203 		error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10204 		error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10205 		error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10206 		error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10207 		error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
10212 	 * prevent the next I915_WRITE from detecting it and printing an error
10217 	return error;
10225 				struct intel_display_error_state *error)
10229 	if (!error)
10235 			   error->power_well_driver);
10238 		err_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
10241 		err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
10242 		err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
10244 			err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
10245 			err_printf(m, "  POS: %08x\n", error->plane[i].pos);
10248 			err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
10250 			err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
10251 			err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
10255 		err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
10256 		err_printf(m, "  POS: %08x\n", error->cursor[i].position);
10257 		err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
10260 	for (i = 0; i < error->num_transcoders; i++) {
10262 			   transcoder_name(error->transcoder[i].cpu_transcoder));
10263 		err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
10264 		err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
10265 		err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
10266 		err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
10267 		err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
10268 		err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
10269 		err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);