Cross Reference: /solaris-x11-s11/open-src/kernel/i915/src/intel

Lines Matching defs:dpll
420 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
422 	return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
3049 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, u32 dpll, u32 fp)
3079 		if ((dpll & 0x7fffffff) == (I915_READ(PCH_DPLL(pll->id)) & 0x7fffffff) &&
3115 		I915_WRITE(PCH_DPLL(pll->id), dpll & ~DPLL_VCO_ENABLE);
3120 		I915_WRITE(PCH_DPLL(pll->id), dpll & ~DPLL_VCO_ENABLE);
4295 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4297 	return (1 << dpll->n) << 16 | dpll->m2;
4300 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4302 	return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4314 		fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4318 		fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4411 	u32 dpll, mdiv;
4417 	bestn = crtc->config.dpll.n;
4418 	bestm1 = crtc->config.dpll.m1;
4419 	bestm2 = crtc->config.dpll.m2;
4420 	bestp1 = crtc->config.dpll.p1;
4421 	bestp2 = crtc->config.dpll.p2;
4500 	dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4503 		dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4505 	dpll |= DPLL_VCO_ENABLE;
4506 	I915_WRITE(DPLL(pipe), dpll);
4532 	u32 dpll;
4534 	struct dpll *clock = &crtc->config.dpll;
4541 	dpll = DPLL_VGA_MODE_DIS;
4544 		dpll |= DPLLB_MODE_LVDS;
4546 		dpll |= DPLLB_MODE_DAC_SERIAL;
4549 		dpll |= (crtc->config.pixel_multiplier - 1)
4554 		dpll |= DPLL_DVO_HIGH_SPEED;
4557 		dpll |= DPLL_DVO_HIGH_SPEED;
4561 		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4563 		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4565 			dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4569 		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4572 		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4575 		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4578 		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4582 		dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4585 		dpll |= PLL_REF_INPUT_TVCLKINBC;
4588 		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4590 		dpll |= PLL_REF_INPUT_DREFCLK;
4592 	dpll |= DPLL_VCO_ENABLE;
4593 	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4604 	I915_WRITE(DPLL(pipe), dpll);
4620 		I915_WRITE(DPLL(pipe), dpll);
4632 	u32 dpll;
4633 	struct dpll *clock = &crtc->config.dpll;
4637 	dpll = DPLL_VGA_MODE_DIS;
4640 		dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4643 			dpll |= PLL_P1_DIVIDE_BY_TWO;
4645 			dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4647 			dpll |= PLL_P2_DIVIDE_BY_4;
4652 		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4654 		dpll |= PLL_REF_INPUT_DREFCLK;
4656 	dpll |= DPLL_VCO_ENABLE;
4657 	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4665 	I915_WRITE(DPLL(pipe), dpll);
4676 	I915_WRITE(DPLL(pipe), dpll);
4910 		intel_crtc->config.dpll.n = clock.n;
4911 		intel_crtc->config.dpll.m1 = clock.m1;
4912 		intel_crtc->config.dpll.m2 = clock.m2;
4913 		intel_crtc->config.dpll.p1 = clock.p1;
4914 		intel_crtc->config.dpll.p2 = clock.p2;
5608 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5610 	return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5621 	uint32_t dpll;
5649 	if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5655 	dpll = 0;
5658 		dpll |= DPLLB_MODE_LVDS;
5660 		dpll |= DPLLB_MODE_DAC_SERIAL;
5662 	dpll |= (intel_crtc->config.pixel_multiplier - 1)
5666 		dpll |= DPLL_DVO_HIGH_SPEED;
5668 		dpll |= DPLL_DVO_HIGH_SPEED;
5671 	dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5673 	dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5675 	switch (intel_crtc->config.dpll.p2) {
5677 		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5680 		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5683 		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5686 		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5691 		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5693 		dpll |= PLL_REF_INPUT_DREFCLK;
5695 	return dpll | DPLL_VCO_ENABLE;
5709 	u32 dpll = 0, fp = 0, fp2 = 0;
5737 		intel_crtc->config.dpll.n = clock.n;
5738 		intel_crtc->config.dpll.m1 = clock.m1;
5739 		intel_crtc->config.dpll.m2 = clock.m2;
5740 		intel_crtc->config.dpll.p1 = clock.p1;
5741 		intel_crtc->config.dpll.p2 = clock.p2;
5749 		fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5753 		dpll = ironlake_compute_dpll(intel_crtc,
5757 		intel_crtc->config.dpll_hw_state.dpll = dpll;
5764 		pll = intel_get_shared_dpll(intel_crtc, dpll, fp);
5793 		I915_WRITE(PCH_DPLL(pll->id), dpll);
5804 		I915_WRITE(PCH_DPLL(pll->id), dpll);
5901 		/* XXX: Can't properly read out the pch dpll pixel multiplier
6947 	u32 dpll = I915_READ(DPLL(pipe));
6951 	if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6967 			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6970 			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6973 		switch (dpll & DPLL_MODE_MASK) {
6975 			clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6979 			clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6984 				  "mode\n", (int)(dpll & DPLL_MODE_MASK));
6996 			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7000 			if ((dpll & PLL_REF_INPUT_MASK) ==
7007 			if (dpll & PLL_P1_DIVIDE_BY_TWO)
7010 				clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7013 			if (dpll & PLL_P2_DIVIDE_BY_4)
7069 	int dpll;
7077 	dpll = I915_READ(dpll_reg);
7078 	if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7083 		dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7084 		I915_WRITE(dpll_reg, dpll);
7087 		dpll = I915_READ(dpll_reg);
7088 		if (dpll & DISPLAY_RATE_SELECT_FPA1)
7112 		int dpll;
7118 		dpll = I915_READ(dpll_reg);
7119 		dpll |= DISPLAY_RATE_SELECT_FPA1;
7120 		I915_WRITE(dpll_reg, dpll);
7122 		dpll = I915_READ(dpll_reg);
7123 		if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8193 	PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8861 	hw_state->dpll = val;
9523 	/* 830/845 need to leave pipe A & dpll A up */
9884 	/* FIXME: Smash this into the new shared dpll infrastructure. */