Cross Reference: /solaris-x11-s11/open-src/kernel/i915/src/intel

Lines Matching refs:val
369 	uint32_t val;
376 			val = I915_READ(SPLL_CTL);
377 			WARN_ON(!(val & SPLL_PLL_ENABLE));
378 			I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
386 			val = I915_READ(WRPLL_CTL1);
387 			WARN_ON(!(val & WRPLL_PLL_ENABLE));
388 			I915_WRITE(WRPLL_CTL1, val & ~WRPLL_PLL_ENABLE);
396 			val = I915_READ(WRPLL_CTL2);
397 			WARN_ON(!(val & WRPLL_PLL_ENABLE));
398 			I915_WRITE(WRPLL_CTL2, val & ~WRPLL_PLL_ENABLE);
643 	uint32_t reg, val;
697 		val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 |
716 		val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC;
724 	I915_WRITE(reg, val);
854 	uint32_t val = I915_READ(reg);
856 	val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK);
857 	val |= TRANS_DDI_PORT_NONE;
858 	I915_WRITE(reg, val);
1072 	uint32_t val;
1075 	val = I915_READ(DDI_BUF_CTL(port));
1076 	if (val & DDI_BUF_CTL_ENABLE) {
1077 		val &= ~DDI_BUF_CTL_ENABLE;
1078 		I915_WRITE(DDI_BUF_CTL(port), val);
1082 	val = I915_READ(DP_TP_CTL(port));
1083 	val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1084 	val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1085 	I915_WRITE(DP_TP_CTL(port), val);
1179 	uint32_t val = I915_READ(LCPLL_CTL);
1189 	if (val & LCPLL_CD_SOURCE_FCLK)
1192 	if (val & LCPLL_PLL_DISABLE)
1202 	uint32_t val;
1206 		val = I915_READ(DDI_BUF_CTL(port));
1207 		if (val & DDI_BUF_CTL_ENABLE) {
1208 			val &= ~DDI_BUF_CTL_ENABLE;
1209 			I915_WRITE(DDI_BUF_CTL(port), val);
1213 		val = I915_READ(DP_TP_CTL(port));
1214 		val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1215 		val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1216 		I915_WRITE(DP_TP_CTL(port), val);
1223 	val = DP_TP_CTL_ENABLE | DP_TP_CTL_MODE_SST |
1226 		val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
1227 	I915_WRITE(DP_TP_CTL(port), val);
1241 	uint32_t val;
1245 	val = I915_READ(_FDI_RXA_CTL);
1246 	val &= ~FDI_RX_ENABLE;
1247 	I915_WRITE(_FDI_RXA_CTL, val);
1249 	val = I915_READ(_FDI_RXA_MISC);
1250 	val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1251 	val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1252 	I915_WRITE(_FDI_RXA_MISC, val);
1254 	val = I915_READ(_FDI_RXA_CTL);
1255 	val &= ~FDI_PCDCLK;
1256 	I915_WRITE(_FDI_RXA_CTL, val);
1258 	val = I915_READ(_FDI_RXA_CTL);
1259 	val &= ~FDI_RX_PLL_ENABLE;
1260 	I915_WRITE(_FDI_RXA_CTL, val);