Cross Reference: /solaris-x11-s11/open-src/kernel/i915/src/intel

Lines Matching defs:port
65 static enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
74 		return intel_dig_port->port;
84 /* On Haswell, DDI port buffers must be programmed with correct values
90 static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port,
100 	DRM_DEBUG_DRIVER("Initializing DDI buffers for port %c in %s mode\n",
101 			port_name(port),
104 	if (use_fdi_mode && (port != PORT_E))
105 		DRM_ERROR("Programming port %c in FDI mode, this probably will not work.",
106 		port_name(port));
108 	for (i=0, reg=DDI_BUF_TRANS(port); i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
115  * mode and port E for FDI.
119 	int port;
124 	for (port = PORT_A; port < PORT_E; port++)
125 		intel_prepare_ddi_buffers(dev, port, false);
147 				    enum port port)
149 	uint32_t reg = DDI_BUF_CTL(port);
157 	DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
162  * both the DDI port and PCH receiver for the desired DDI buffer settings.
164  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
177 	 * mode set "sequence for CRT port" document:
213 		 * DDI E does not support port reversal, the functionality is
215 		 * port reversal bit */
294 	int port = intel_ddi_get_encoder_port(intel_encoder);
298 	DRM_DEBUG_KMS("Preparing DDI mode on port %c, pipe %c\n",
299 		      port_name(port), pipe_name(pipe));
770 	enum port port = intel_ddi_get_encoder_port(intel_encoder);
776 	temp |= TRANS_DDI_SELECT_PORT(port);
867 	enum port port = intel_ddi_get_encoder_port(intel_encoder);
875 	if (port == PORT_A)
906 	enum port port = intel_ddi_get_encoder_port(encoder);
910 	tmp = I915_READ(DDI_BUF_CTL(port));
915 	if (port == PORT_A) {
937 			    == TRANS_DDI_SELECT_PORT(port)) {
944 	DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
953 	enum port port = I915_MAX_PORTS;
959 		port = PORT_A;
966 				port = i;
969 	if (port == I915_MAX_PORTS) {
970 		DRM_ERROR("Pipe %c enabled on an unknown port\n",
974 		ret = I915_READ(PORT_CLK_SEL(port));
975 		DRM_DEBUG_KMS("Pipe %c connected to port %c using clock "
976 			      "0x%08x\n", pipe_name(pipe), port_name(port),
1018 	enum port port = intel_ddi_get_encoder_port(intel_encoder);
1023 			   TRANS_CLK_SEL_PORT(port));
1042 	enum port port = intel_ddi_get_encoder_port(intel_encoder);
1053 	I915_WRITE(PORT_CLK_SEL(port), intel_crtc->ddi_pll_sel);
1061 		if (port != PORT_A)
1070 	enum port port = intel_ddi_get_encoder_port(intel_encoder);
1075 	val = I915_READ(DDI_BUF_CTL(port));
1078 		I915_WRITE(DDI_BUF_CTL(port), val);
1082 	val = I915_READ(DP_TP_CTL(port));
1085 	I915_WRITE(DP_TP_CTL(port), val);
1088 		intel_wait_ddi_buf_idle(dev_priv, port);
1096 	I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1107 	enum port port = intel_ddi_get_encoder_port(intel_encoder);
1115 		/* In HDMI/DVI mode, the port width, and swing/emphasis values
1117 		 * enabling the port.
1119 		I915_WRITE(DDI_BUF_CTL(port),
1125 		if (port == PORT_A)
1201 	enum port port = intel_dig_port->port;
1205 	if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
1206 		val = I915_READ(DDI_BUF_CTL(port));
1209 			I915_WRITE(DDI_BUF_CTL(port), val);
1213 		val = I915_READ(DP_TP_CTL(port));
1216 		I915_WRITE(DP_TP_CTL(port), val);
1217 		POSTING_READ(DP_TP_CTL(port));
1220 			intel_wait_ddi_buf_idle(dev_priv, port);
1227 	I915_WRITE(DP_TP_CTL(port), val);
1228 	POSTING_READ(DP_TP_CTL(port));
1231 	I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
1232 	POSTING_READ(DDI_BUF_CTL(port));
1303 	int port = intel_ddi_get_encoder_port(encoder);
1308 	if (port == PORT_A)
1325 void intel_ddi_init(struct drm_device *dev, enum port port)
1360 	intel_dig_port->port = port;
1361 	intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
1364 	intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
1385 		intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);